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TLC5911PZP Datasheet(PDF) 6 Page - Texas Instruments |
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TLC5911PZP Datasheet(HTML) 6 Page - Texas Instruments |
6 / 30 page TLC5911 LED DRIVER SLLS402 – DECEMBER 1999 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions (Continued) TERMINAL I/O DESCRIPTION NAME NO. I/O DESCRIPTION DIN0 – DIN9 76,77,78,79,80, 81,82,83,84,85 I Input for 10 bit parallel data (port A). These terminals are inputs for shift register for gray scale data, brightness control, and dot correction data. The register selected is determined by RSEL0, 1. DOUT0 – DOUT9 41,42,43,44,45, 46,47,48,49,50 O Output for 10 bit parallel data (port A). These terminals are outputs for shift register for gray scale data, brightness control, and dot correction data. The register selected is determined by RSEL0, 1. DPOL 96 I Selects the valid edge of DCLK. When DPOL is high, the rising edge of DCLK is valid. When DPOL is low, the falling edge of DCLK is valid. GNDANA 28 Analog ground (Internally connected to GNDLOG and GNDLED) GNDLOG 98 Logic ground (Internally connected to GNDANA and GNDLED) GNDLED 1,4,7,10,13, 16,19,22,25 LED driver ground (Internally connected to GNDANA and GNDLED) GSCLK 68 I Clock input for gray scale. When MAG0 through MAG2 are all low, GSCLK is used for pulse width control. When MAG0 through MAG2 are not low, GSCLK is used for PLL timing control. The gray scale display is accomplished by lighting the LED until the number of GSCLK or PLL clocks counted is equal to the data latched. GSPOL 69 I Select the valid edge of GSCLK. When GSPOL is high, the rising edge of GSCLK is valid. When GSPOL is low, the falling edge of GSCLK is valid. IREF 32 I/O Constant current value setting. LED current is set to the desired value by connecting an external resistor between IREF and GND. The 38 times current is compared to current across the external resistor sink on the output terminal. LEDCHK 58 I LED disconnection detection enable. When LEDCHK is high, the LED disconnection detection is enabled and XDOWN2 is valid. When LEDCHK is low, the LED disconnection detection is disabled. MAG0 – MAG2 73,72,71 I PLL multiple ratio setting. The clock frequency generated by PLL referenced to GSCLK is set . NC 57 No internal connection OUT0 – DOUT15 2,3,5,6,8,9,11, 12,14,15,17,18, 20,21,23,24 O Constant current output PDOUT 70 I/O Resistor connection for PLL feedback adjustment RBIAS 74 I/O Resistor connection for PLL oscillation frequency setting RSEL0 RSEL1 60 59 I Input/output port selection and shift register data latch switching. When RSEL1 is low and RSEL0 is low, the gray scale data shift register latch is selected to port A, and the dot correction register latch is selected to port B. When RSEL1 is low and RSEL0 is high, the brightness control register latch is selected to port A, and the dot correction register latch is selected to port B. When RSEL1 is high and RSEL0 is low, the dot correction register latch is selected to port A and no register latch is selected to port B. TEST1 – TEST3 97,99,100 I TEST. Factory test terminal. These terminals should be connected to GND. THERMAL PAD Package bottom Heat sink pad. This pad is connected to the lowest potential IC or thermal layer. TSENA 31 I TSD enable. When TSENA is high, TSD is enabled. When TSENA is low, TSD is disabled. VCCANA 33 Analog power supply voltage VCCLOG 93 Logic power supply voltage VCCLED 26 LED driver power supply voltage VCOIN 75 I/O Capacitance connection for PLL feedback adjustment WDCAP 30 I/O WDT detection time adjustment. WDT detection time is adjusted by connecting a capacitor between WDCAP and GND. When WDCAP is directly connected to GND, the WDT function is disabled. In this case, WDTRG should be tied to high or low level. |
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