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TLC7225CDW Datasheet(PDF) 9 Page - Texas Instruments |
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TLC7225CDW Datasheet(HTML) 9 Page - Texas Instruments |
9 / 21 page TLC7225C, TLC7225I QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS SLAS109B – OCTOBER 1996 – REVISED FEBRUARY 2001 9 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 APPLICATION INFORMATION output buffer Each voltage-mode DAC output is buffered by a unity-gain noninverting amplifier. This buffer amplifier is capable of developing 10 V across a 2-k Ω load and can drive capacitive loads of 3300 pF. The TLC7225 can be operated as a single or dual supply; operating with dual supplies results in enhanced performance in some parameters which cannot be achieved with a single-supply operation. In a single supply operating (VSS = 0 V = AGND) the sink capability of the amplifier, which is normally 400 µA, is reduced as the output voltage nears AGND. The full sink capability of 400 µA is maintained over the full output voltage range by tying VSS to –5 V. This is indicated in Figure 3. Settling time for negative-going output signals approaching AGND is similarly affected by VSS. Negative-going settling time for single supply operation is longer than for dual supply operation. Positive-going settling-time is not affected by VSS. Additionally, the negative VSS gives more headroom to the output amplifiers which results in better zero code performance and improved slew rate at the output than can be obtained in the single-supply mode. digital inputs The TLC7225 digital inputs are compatible with either TTL or 5-V CMOS levels. To minimize power supply currents, it is recommended that the digital input voltages be driven as close to the supply rails (VDD and DGND) as practically possible. interface logic information The TLC7225 contains two registers per DAC, an input register and a DAC register. Address lines A0 and A1 select which input register accepts data from the input port. When the WR signal is low, the input latches of the selected DAC are transparent. The data is latched into the addressed input register on the rising edge of WR. Table 1 shows the addressing for the input registers on the TLC7225. Table 1. TLC7225 Addressing CONTROL INPUTS SELECTED INPUT REGISTER A1 A0 REGISTER L L DAC A input register L H DAC B input register H L DAC C input register H H DAC D input register Only the data held in the DAC register determines the analog output of the converter. The LDAC signal is common to all four DACs and controls the transfer of information from the input registers to the DAC registers. Data is latched into all four DAC registers simultaneously on the rising edge of LDAC. The LDAC signal is level triggered and, therefore, the DAC registers may be made transparent by tying LDAC low (the outputs of the converters responds to the data held in their respective input latches). LDAC is an asynchronous signal and is independent of WR. This is useful in many applications. However, in systems where the asynchronous LDAC can occur during a write cycle (or vice versa) care must be taken to ensure that incorrect data is not latched through to the output. In other words, if LDAC is activated prior to the rising edge of WR (or WR occurs during LDAC), then LDAC must stay low for a time of tw2 or longer after WR goes high to ensure that the correct data is latched through to the output. Table 2 shows the truth table for TLC7225 operation. Figure 5 shows the input control logic for the device and the write cycles timing diagram is shown in Figure 1. |
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