TPA0142

2-W STEREO AUDIO POWER AMPLIFIER

WITH DC VOLUME CONTROL

SLOS248B – JUNE 1999 – REVISED MARCH 2000

3

POST OFFICE BOX 655303

AVAILABLE OPTIONS

PACKAGED DEVICE

TA

TSSOP†

(PWP)

–40

°C to 85°C

TPA0142PWP

† The PWP package is available taped and reeled. To order a taped and reeled part,

add the suffix R to the part number (e.g., TPA0142PWPR).

Terminal Functions

TERMINAL

I/O

DESCRIPTION

NAME

NO.

I/O

DESCRIPTION

BYPASS

11

Tap to voltage divider for internal mid-supply bias generator

CLK

17

I

If a 47-nF capacitor is attached, the TPA0142 generates an internal clock. An external clock can override

the internal clock input to this terminal.

GND

1, 12

13, 24

Ground connection for circuitry. Connected to thermal pad

LHPIN

6

I

Left channel headphone input, selected when SE/BTL is held high

LIN

10

I

Common left input for fully differential input. AC ground for single-ended inputs

LLINEIN

5

I

Left channel line negative input, selected when SE/BTL is held low

LOUT+

4

O

Left channel positive output in BTL mode and positive output in SE mode

LOUT–

9

O

Left channel negative output in BTL mode and high-impedance in SE mode

PCB ENABLE

2

I

If this terminal is high, the detection circuitry for PC-BEEP is overridden and passes PC-BEEP through the

amplifier, regardless of its amplitude. If PCB ENABLE is floating or low, the amplifier continues to operate

normally.

PC-BEEP

14

I

The input for PC Beep mode. PC-BEEP is enabled when a > 1-V (peak-to-peak) square wave is input to

PC-BEEP or PCB ENABLE is high.

PVDD

7, 18

I

Power supply for output stage

RHPIN

20

I

Right channel headphone input, selected when SE/BTL is held high

RIN

8

I

Common right input for fully differential input. AC ground for single-ended inputs

RLINEIN

23

I

Right channel line input, selected when SE/BTL is held low

ROUT+

21

O

Right channel positive output in BTL mode and positive output in SE mode

ROUT–

16

O

Right channel negative output in BTL mode and high-impedance in SE mode

SE/BTL

15

I

Input MUX control input. When this terminal is held high, the LHPIN or RHPIN and SE output is selected.

When this terminal is held low, the LLINEIN or RLINEIN and BTL output are selected.

SHUTDOWN

22

I

When held low, this terminal places the entire device, except PC-BEEP detect circuitry, in shutdown mode.

VDD

19

I

Analog VDD input supply. This terminal needs to be isolated from PVDD to achieve highest performance.

VOLUME

3

I

VOLUME detects the dc level at the terminal and sets the gain for 31 discrete steps covering a range of

20 dB to –40 dB for dc levels of 0.15 V to 3.54. When the dc level is over 3.54 V, the device is muted.