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TSB11LV01PT Datasheet(PDF) 7 Page - Texas Instruments |
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TSB11LV01PT Datasheet(HTML) 7 Page - Texas Instruments |
7 / 21 page TSB11LV01 3-V 1-PORT IEEE 1394-1995 CABLE TRANSCEIVER/ARBITER SLLS232B – MARCH 1996 – REVISED MAY 1997 7 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions (continued) TERMINAL I/O TYPE DESCRIPTION NAME NO. I/O TYPE DESCRIPTION PC0, PC1, PC2 4, 5, 6 I CMOS Power class indicators. the PC signals set the bit values of the three power class bits in the Self-ID packet (bits 21, 22, and 23). These bits can be pro- grammed by tying the terminals to VCC (high) or to GND (low). PLLFLT 42 I CMOS PLL filter. PLLFLT is connected to a 0.1- µF capacitor and then to AGND to complete the internal lag-lead filter. This filter is required for stable opera- tion of the frequency multiplier PLL running off of the crystal oscillator. PLLGND 39, 40 – Supply PLL circuit ground. The PLLGND terminals should be tied to the low-imped- ance circuit board ground plane. PLLVCC 41 – Supply PLL circuit power. PLLVCC supplies power to the PLL portion of the device. It is recommended that a combination of high-frequency decoupling capaci- tors be connected to PLLVCC (i.e., paralleled 0.1 µF and 0.001 µF). Lower frequency 10- µF filtering capacitors can also be used. These supply pins are separated internally in the device to provide noise isolation. These ter- minals should also be tied at a low impedance point on the circuit board. Individual filtering networks for each is desired. PWRDN 43 I CMOS Powerdown. When asserted high, PWRDN turns off all internal circuitry except the CNA monitor circuits that drive the CNA terminal. R1, R0 31, 32 – Bias Current setting resistor. An internal reference voltage is applied to a resistor connected between these two terminals to set the operating current and the cable driver output current. A low TCR 6 k Ω ±5% resistor should be used to meet the IEEE 1394-1995 standard requirements for output voltage limits. RESET 46 I CMOS Reset. When RESET is asserted low (active), a bus reset condition is set on the active cable ports and the the internal logic is reset to the reset start state. An internal pullup resistor, which is connected to VCC, is provided so only an external delay capacitor is required. This input is a standard logic buffer and can also be driven by an open-drain logic output buffer. SYSCLK 12 O CMOS System clock. SYSCLK provides a 49.152-MHz clock signal, which is syn- chronized with the data transfers, to the link. TESTM1, TESTM2 48, 47 I CMOS Test mode control. TESTM1 and TESTM2 are used during manufacturing test and should be tied to VCC. TPA + 36 I/O Cable Port cable pair A. TPA is the port A connection to the twisted pair cable. Board traces from these terminal should be kept matched and as short as TPA – 35 Board traces from these terminal should be ke t matched and as short as possible to the external load resistors and to the cable connector. TPB + 34 I/O Cable Port cable pair B. TPB is the port B connection to the twisted pair cable. Board traces from these terminal should be kept matched and as short as TPB – 33 Board traces from these terminal should be ke t matched and as short as possible to the external load resistors and to the cable connector. TPBIAS 25 O Cable Twisted-pair bias. TPBIAS provides the 1.86-V nominal bias voltage need- ed for proper operation of the twisted-pair cable drivers and receivers and for sending a valid cable connection signal to the remote nodes. XO, XI 37, 38 – Crystal Crystal oscillator. X0 and X1 connect to a 24.576-MHz parallel resonant fundamental mode crystal. The optimum values for the external shunt ca- pacitors are dependent on the specifications of the crystal used. The sug- gested values of 12 pF are appropriate for a crystal with 15 pF specified loads. |
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