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TSB12LV22PZP Datasheet(PDF) 5 Page - Texas Instruments

No. de pieza TSB12LV22PZP
Descripción Electrónicos  OHCI-Lynx PCI-BASED IEEE 1394 HOST CONTROLLER
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TSB12LV22PZP Datasheet(HTML) 5 Page - Texas Instruments

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TSB12LV22
OHCI-Lynx PCI-BASED IEEE 1394 HOST CONTROLLER
SLLS290 – JULY 1998
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
This section describes the OHCI-Lynx terminal functions. The terminals are grouped in tables by functionality for
convenient reference.
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
NO.
I/O
DESCRIPTION
Power Supply
GND
1,11,24,30,42,50,
60,75,83,94,100
I
Device ground terminals
VCC
9,13,20,35,46,55,
70,80,91,96
I
3.3-V power supply terminals
VCCS
6,87
I
Clamp rail power input.; Provides 5 V tolerance for non PCI I/Os
VCCP
16,39,63
I
PCI signaling clamp rail power input. PCI signals clampled per PCI specification
PCI System
PCI_CLK
12
I/O
PCI Bus Clock. Provides timing for all transactions on the PCI bus. All PCI signals are sampled at
rising edge of PCLK.
PCI_RST
10
I/O
PCI Reset. When the PCI bus reset is asserted the OHIC1-Lynx 3-states all output buffers and resets
internal registers. When asserted, the device is completely nonfunctional. After deasserting RST,
the OHCI-Lynx is in its default state.
PCI_INTA
8
I/O
PCI Interrupt A. The OHCI-Lynx drives this shared interrupt signal low when there is a pending
internal interrupt event that has occurred.
PCI Address and Data
PCI_AD31 –
PCI_AD0
18,19,21–23,
25–27,31–34,
36–38,40,54,
56–59,61,62,64,
66–69,71–74
I/O
PCI Address/Data Bus. These signals make up the multiplexed PCI address and data bus on the
PCI interface during the address phase of a PCI cycle, AD31:0 contains a 32-bit address or other
destination information. During the data phase AD31:0 contains data.
PCI_C/BE0
PCI_C/BE1
PCI_C/BE2
PCI_C/BE3
65,
53,
41,
28
I/O
PCI Bus Commands and Byte Enables. The command and byte enable signals are multiplexed on
the same PCI terminals. During the address phase of a bus cycle C/BE3:0 defines the bus command.
During the data phase, this four-bit bus is used as byte enables.
PCI_PAR
52
I/O
PCI Parity. In all PCI bus read and write cycles, the OHCI-Lynx calculates even parity across the AD
and C/BE buses. As an initiator during PCI cycles, the OHCI-Lynx outputs this parity indicator with
a one PCLK delay. As a target during PCI cycles, the calculated parity is compared to the initiator’
parity indicator; a miscompare can result in a parity error assertion (PERR).
PCI Interface Control
PCI_DEVSEL
47
I/O
PCI Device Select. The OHCI-Lynx will assert this signal to claim a PCI cycle as the target device.
As a PCI initiator, the OHCI-Lynx monitors this signal until a target responds. If no target responds
before time-out occurs, then the OHCI-Lynx will terminate the cycle with an initiator abort.
PCI_FRAME
43
I/O
PCI Cycle Frame. This signal is driven by the initiator of a PCI bus cycle. FRAME is asserted to
indicate that a bus transaction is beginning, and data transfers continue until while this signal is
asserted. When FRAME is deasserted, the PCI bus transaction is in the final data phase.
PCI_GNT
14
I
PCI Bus Grant. This signal is driven by the PCI bus arbiter to grant the OHCI-Lynx access to the PCI
bus after the current data transaction has completed. This signal may or may not follow a PCI bus
request depending upon the PCI bus parking algorithm.
PCI_IDSEL
29
I
Initialization Device Select. IDSEL selects the OHCI-Lynx during configuration space accesses.
IDSEL can be connected to one of the upper 24 PCI address lines on the PCI bus.
PCI_IRDY
44
I/O
PCI Initiator Ready. IRDY indicates the PCI bus initiator’s ability to complete the current data phase
of the transaction. A data phase is completed upon a rising edge of PCLK where both IRDY and
TRDY are asserted; until which wait states are inserted.
PCI_STOP
48
I/O
PCI Cycle Stop Signal. This signal is driven by a PCI target to request the initiator to stop the current
PCI bus transaction. This signal is used for target disconnects, and is commonly asserted by target
devices which do not support burst data transfers.


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