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TSB41LV01 Datasheet(PDF) 8 Page - Texas Instruments |
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TSB41LV01 Datasheet(HTML) 8 Page - Texas Instruments |
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8 / 49 page  TSB41LV01 IEEE 1394A ONE-PORT CABLE TRANSCEIVER/ARBITER SLLS365 – AUGUST 1999 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions (Continued) TERMINAL I/O DESCRIPTION NAME NO. I/O DESCRIPTION ISO 23 I Link interface isolation control input. This pin controls the operation of output differentiation logic on the CTL and D pins. If an optional Annex J type isolation barrier is implemented between the TSB41LV01 and LLC, the ISO pin should be tied low to enable the differentiation logic. If no isolation barrier is implemented (direct connection), or TI bus holder isolation is implemented, the ISO pin should be tied high to disable the differentiation logic. For additional information refer to TI application note Serial Bus Galvanic Isolation, SLLA011. LPS 15 I Link power status input. This pin is used to monitor the active/power status of the link layer controller and to control the state of the Phy-LLC interface. This pin should be connected to either the VDD supplying the LLC through a 10 k Ω resistor, or to a pulsed output which is active when the LLC is powered. A pulsed signal should be used when an isolation barrier exists between the LLC and Phy. (See Figure 1). The LPS input is considered inactive if it is sampled low by the Phy for more than 2.6 µs (128 SYSCLK cycles), and is considered active otherwise (i.e., asserted steady high or an oscillating signal with a low time less than 2.6 µs). The LPS input must be high for at least 21 ns in order to be guaranteed to be observed as high by the Phy. When the TSB41LV01 detects that LPS is inactive, it will place the Phy-LLC interface into a low-power reset state. In the reset state, the CTL and D outputs are held in the logic zero state and the LREQ input is ignored; however, the SYSCLK output remains active. If the LPS input remains low for more than 26 µs (1280 SYSCLK cycles), the Phy-LLC interface is put into a low-power disabled state in which the SYSCLK output is also held inactive. The Phy-LLC interface is placed into the disabled state upon hardware reset. The LLC is considered active only if both the LPS input is active and the LCtrl register bit is set to 1, and is considered inactive if either the LPS input is inactive or the LCtrl register bit is cleared to 0. LREQ 1 I LLC Request input. The LLC uses this input to initiate a service request to the TSB41LV01. Bus holder is built into this terminal. PC0 PC1 PC2 20 21 22 I Power class programming inputs. On hardware reset, these inputs set the default value of the power class indicated during self-ID. Programming is done by tying these pins high or low. Refer to Table 2 for encoding. PD 14 I Power-down input. A high on this pin turns off all internal circuitry except the cable-active monitor circuits, which controls the CNA output. Asserting the PD input high also activates an internal pull-down on the RESET terminal so as to force a reset of the internal control logic. PLLGND 57, 58 – PLL circuit ground pins. These pins should be tied together to the low impedance circuit board ground plane. PLLVDD 56 – PLL circuit power pins. A combination of high frequency decoupling capacitors near each pin are suggested, such as paralleled 0.1 µF and 0.001 µF. Lower frequency 10 µF filtering capacitors are also recommended. These supply pins are separated from DVDD and AVDD internal to the device to provide noise isolation. They should be tied at a low-impedance point on the circuit board. R0 R1 40 41 – Current setting resistor pins. These pins are connected to an external resistance to set the internal operating currents and cable driver output currents. A resistance of 6.30 k Ω ±0.5% is required to meet the IEEE Std 1394-1995 output voltage limits. RESET 53 I Logic reset input. Asserting this pin low resets the internal logic. An internal pull-up resistor to VDD is provided so only an external delay capacitor is required for proper power-up operation (see power-up reset in the APPLICATION INFORMATION section). The RESET terminal also incorporates an internal pull-down which is activated when the PD input is asserted high. This input is otherwise a standard logic input, and may also be driven by an open-drain type driver. SE 28 I Test control input. This input is used in manufacturing test of the TSB41LV01. For normal use this pin should be tied to GND through a 1-k Ω pulldown resistor. SM 29 I Test control input. This input is used in manufacturing test of the TSB41LV01. For normal use this pin should be tied to GND. SYSCLK 2 O System clock output. Provides a 49.152 MHz clock signal, synchronized with data transfers, to the LLC. |
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