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UC1826 Datasheet(PDF) 7 Page - Texas Instruments

No. de pieza UC1826
Descripción Electrónicos  Secondary Side Average Current Mode Controller
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Fabricante Electrónico  TI [Texas Instruments]
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UC1826 Datasheet(HTML) 7 Page - Texas Instruments

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7
positive sense voltage (VSP) connects to the voltage
error amplifier inverting terminal (VA-), the return lead for
the on-chip reference is used as the negative sense
(VSM). The current is sensed across the shunt resistor,
RS. The voltage across the shunt resistor is level shifted
up so that the maximum voltage across Rs corresponds
to the voltage error amplifier Voh.
Figure 4 shows one recommended voltage and current
sensing scheme when VEE is connected to GND. The
signal ground is the negative sense point for the output
voltage and the positive sense point for the output cur-
rent. VEE is the negative supply for the current sense
amplifier. When it is separated from GND, it extends the
current sense amplifier’s common mode input voltage
range to include VEE which is approximately
−0.7V
below ground. The resistor RADJ is used for load sharing.
The unit which is the master will force VADJ to 1.0V.
Therefore, the regulated voltage being sensed is actually
RADJ
R1
+ RADJ
VSM = 0V, VADJ = 1V (master), VREF = 5V
RADJ
R1
+ RADJ
The voltage at ADJ on the slave chips will increase forc-
ing their load currents to increase to match the master.
The AC frequency response of the voltage error amplifier
is shown in Figure 5.
Startup and Shutdown: Isolated power up can be
accomplished using the UCC1889. Application Note
U-149 is available for additional information.
The UC1826 offers several features that enhance startup
and shutdown. Soft start is accomplished by connecting
RUN to VA+ and a capacitor to ground. The resulting RC
rise time on the VA+ pin initiates a soft start. It can also
be accomplished by connecting RUN to ILIM. When RUN
is low it will command zero load current, guaranteeing a
soft start. The undervoltage lockout (UVLO) is a logical
AND of ENBL < 2.5V, SEQ > 2.5V, VCC > 8.4V and
Figure 3. Oscillator Synchronization
Connection Diagram
Figure 4. Voltage and Current Sense VEE Tied to GND
VSP
− VSM = (VREF − VADJ)
· () + VADJ
VSP = 4
· () + 1V
UC1826
UC2826
UC3826
CIRCUIT BLOCK DESCRIPTION (cont.)
∅ ≈
m
Figure 5. AC Frequency Response of the Voltage
Error Amplifier
UDG-95015
UDG-95016


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