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ISL12008IB8Z Datasheet(PDF) 10 Page - Intersil Corporation

No. de pieza ISL12008IB8Z
Descripción Electrónicos  I2C Real Time Clock with Battery Backup
Download  19 Pages
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Fabricante Electrónico  INTERSIL [Intersil Corporation]
Página de inicio  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

ISL12008IB8Z Datasheet(HTML) 10 Page - Intersil Corporation

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10
FN6690.1
September 26, 2008
Real Time Clock Registers
Addresses [00h to 06h, and 1Fh]
RTC REGISTERS (SC, MN, HR, DW, DT, MO, YR, SS)
These registers depict BCD representations of the time. As
such, SC (Seconds, address 00h) and MN (Minutes,
address 01h) range from 0 to 59, HR (Hour, address 02h) is
in 24-hour mode with a range from 0 to 23, DW (Day of the
Week, address 03h) is 1 to 7, DT (Date, address 04h) is 1 to
31, MO (Month, address 05h) is 1 to 12, YR (Year, address
06h) is 0 to 99, and SS (Sub-Seconds/Hundredths of
Seconds, address 1Fh) is 0 to 99. The default for all the time
keeping bits are set to “0” at power up.
Bit D7 of SC register contain the crystal enable/disable bit
(ST). Setting ST to “1” will disable the crystal from oscillating
and stop the counting in RTC register. When the ST bit is set
to “1”, it will casue the OF bit to set to “1” due to no crystal
oscillation on the X1 pin. The ST bit is set to “0” on power-up
for normal operation.
Bit D7 of MN register contain the Oscillator Fail Indicator bit
(OF). This bit is set to a “1” when the X1 pin has no
oscillation. This bit can be reset when the X1 has crystal
oscillation and a write to “0”. This bit can only be written as
“0” and not as a “1”. The OF bit is set to “1” at power-up from
a complete power down (VDD and VBAT are removed).
Address 9, bit 7 is also used as the OF bit for DS1340
compatibility, and the two OF bits are interchangable.
Bits D6 and D7 of HR register (century/hours register)
contain the century enable bit (CEB) and the century bit
(CB). Setting CEB to a '1' will cause CB to toggle, either from
'0' to '1' or from '1' to '0' at the turn of the century (depending
upon its initial state). If CEB is set to a '0', CB will not toggle.
The DW register provides a Day of the Week status and uses
three bits DW2 to DW0 to represent the seven days of the
week. The counter advances in the cycle 1-2-3-4-5-6-7-1-2-
… The assignment of a numerical value to a specific day of
the week is arbitrary and may be decided by the system
software designer.
TABLE 1. REGISTER MEMORY MAP
ADDR. SECTION
REG
NAME
BIT
REG
7
6
5
4
3
2
1
0
RTC
RANGE
DEFAULT
00h
RTC
SC
ST
SC22
SC21
SC20
SC13
SC12
SC11
SC10
0 to 59
00h
01h
MN
OF
MN22
MN21
MN20
MN13
MN12
MN11
MN10
0 to 59
80h
02h
HR
CEB
CB
HR21
HR20
HR13
HR12
HR11
HR10
0 to 23
00h
03h
DW
00000
DW12
DW11
DW10
1 to 7
00h
04h
DT
0
0
DT21
DT20
DT13
DT12
DT11
DT10
1 to 31
00h
05h
MO
0
0
0
MO20
MO13
MO12
MO11
MO10
1 to 12
00h
06h
YR
YR23
YR22
YR21
YR20
YR13
YR12
YR11
YR10
0 to 99
00h
07h
Control
DTR
OUT
FT
DTR5
DTR4
DTR3
DTR2
DTR1
DTR0
N/A
80h
08h
INT
0
ALME
LPMODE
00000
N/A
00h
09h
OF
OF
0000000
N/A
80h
0Ah
ATR
BMATR1
BMATR0
ATR5
ATR4
ATR3
ATR2
ATR1
ATR0
N/A
00h
0Bh
Status
SR
ARST
XSTOP
RESEAL
0
0
ALM
BAT
RTCF
N/A
03h
0Ch
Alarm0
SCA
ESCA
ASC22
ASC21
ASC20
ASC13
ASC12
ASC11
ASC10
00 to 59
00h
0Dh
MNA
EMNA
AMN22
AMN21
AMN20
AMN13
AMN12
AMN11
AMN10
00 to 59
00h
0Eh
HRA
EHRA
0
AHR21
AHR20
AHR13
AHR12
AHR11
AHR10
0 to 23
00h
0Fh
DTA
EDTA
0
ADT21
ADT20
ADT13
ADT12
ADT11
ADT10
1 to 31
00h
10h
MOA
EMOA
0
0
AMO20
AMO13
AMO12
AMO11
AMO10
1 to 12
00h
11h
DWA
EDWA
0000
ADW12
ADW11
ADW10
1 to 7
00h
1Fh
(Read-
Only)
RTC
SS
SS23
SS22
SS21
SS20
SS13
SS12
SS11
SS10
0 to 99
00h
NOTE: 0 = must be set to‘0’
ISL12008


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