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CS2200P-CZZR Datasheet(PDF) 2 Page - Cirrus Logic |
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CS2200P-CZZR Datasheet(HTML) 2 Page - Cirrus Logic |
2 / 24 page CS2200-OTP DS842F1 2 TABLE OF CONTENTS 1. PIN DESCRIPTION ................................................................................................................................. 4 2. TYPICAL CONNECTION DIAGRAM ..................................................................................................... 5 3. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 6 RECOMMENDED OPERATING CONDITIONS .................................................................................... 6 ABSOLUTE MAXIMUM RATINGS ........................................................................................................ 6 DC ELECTRICAL CHARACTERISTICS ................................................................................................ 6 AC ELECTRICAL CHARACTERISTICS ................................................................................................ 7 4. ARCHITECTURE OVERVIEW ............................................................................................................... 8 4.1 Delta-Sigma Fractional-N Frequency Synthesizer ........................................................................... 8 5. APPLICATIONS ..................................................................................................................................... 9 5.1 One Time Programmability .............................................................................................................. 9 5.2 Timing Reference Clock Input .......................................................................................................... 9 5.2.1 Internal Timing Reference Clock Divider ................................................................................. 9 5.2.2 Crystal Connections (XTI and XTO) ...................................................................................... 10 5.2.3 External Reference Clock (REF_CLK) .................................................................................. 10 5.3 Output to Input Frequency Ratio Configuration ............................................................................. 11 5.3.1 User Defined Ratio (RUD) ..................................................................................................... 11 5.3.2 Ratio Modifier (R-Mod) .......................................................................................................... 11 5.3.3 Effective Ratio (REFF) .......................................................................................................... 11 5.3.4 Ratio Configuration Summary ............................................................................................... 12 5.4 PLL Clock Output ........................................................................................................................... 13 5.5 Auxiliary Output .............................................................................................................................. 14 5.6 Mode Pin Functionality ................................................................................................................... 14 5.6.1 M1 and M0 Mode Pin Functionality ....................................................................................... 14 5.6.2 M2 Mode Pin Functionality .................................................................................................... 15 5.6.2.1 M2 Configured as Output Disable .............................................................................. 15 5.6.2.2 M2 Configured as R-Mod Enable .............................................................................. 15 5.6.2.3 M2 Configured as AuxOutSrc Override ..................................................................... 15 5.7 Clock Output Stability Considerations ............................................................................................ 16 5.7.1 Output Switching ................................................................................................................... 16 5.7.2 PLL Unlock Conditions .......................................................................................................... 16 5.8 Required Power Up Sequencing for Programmed Devices ........................................................... 16 6. PARAMETER DESCRIPTIONS ........................................................................................................... 17 6.1 Modal Configuration Sets ............................................................................................................... 17 6.1.1 R-Mod Selection (RModSel[1:0]) ...........................................................................................17 6.1.2 Auxiliary Output Source Selection (AuxOutSrc[1:0]) ............................................................. 18 6.2 Ratio 0 - 3 ...................................................................................................................................... 18 6.3 Global Configuration Parameters ................................................................................................... 18 6.3.1 AUX PLL Lock Output Configuration (AuxLockCfg) .............................................................. 18 6.3.2 Reference Clock Input Divider (RefClkDiv[1:0]) .................................................................... 18 6.3.3 Enable PLL Clock Output on Unlock (ClkOutUnl) ................................................................. 19 6.3.4 M2 Pin Configuration (M2Config[2:0]) ................................................................................... 19 7. CALCULATING THE USER DEFINED RATIO .................................................................................... 20 7.1 12.20 Format .................................................................................................................................. 20 8. PROGRAMMING INFORMATION ........................................................................................................ 21 9. PACKAGE DIMENSIONS .................................................................................................................... 22 THERMAL CHARACTERISTICS ......................................................................................................... 22 10. ORDERING INFORMATION .............................................................................................................. 23 11. REVISION HISTORY .......................................................................................................................... 24 |
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