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CS5372A Datasheet(PDF) 11 Page - Cirrus Logic |
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CS5372A Datasheet(HTML) 11 Page - Cirrus Logic |
11 / 32 page CS5371A CS5372A DS748F2 11 DIGITAL CHARACTERISTICS (CONT.) Notes: 20. MCLK is generated by the digital filter. If MCLK is disabled, the device automatically enters a power- down state. 21. MSYNC is generated by the digital filter and is latched on MCLK falling edge, synchronization instant (t0) is on the next MCLK rising edge. 22. Decimated, filtered, and offset-corrected 24-bit output word from the digital filter. Parameter Symbol Min Typ Max Unit Master Clock Input MCLK Frequency (Note 20)fCLK -2.048 - MHz MCLK Period (Note 20)tmclk -488 - ns MCLK Duty Cycle (Note 9)MCLKDC 40 - 60 % MCLK Rise Time (Note 9)tRISE -- 50 ns MCLK Fall Time (Note 9)tFALL -- 50 ns MCLK Jitter (in-band or aliased in-band) (Note 9)MCLKIBJ -- 300 ps MCLK Jitter (out-of-band) (Note 9)MCLKOBJ -- 1 ns Master Sync Input MSYNC Setup Time to MCLK Falling (Note 9, 21)tmss 20 122 - ns MSYNC Period (Note 9, 21)tmsync 40 976 - ns MSYNC Hold Time after MCLK Falling (Note 9, 21)tmsh 20 122 - ns MDATA Output MDATA Output Bit Rate fmdata - 512 - kbits/s MDATA Output Bit Period tmdata - 1953 - ns MDATA Output One’s Density Range (Note 9)MDATOD 14 - 86 % Full-scale Output Code (Note 22)MDATFS 0xA2EBE0 - 0x5D1420 |
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