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SA53 Datasheet(PDF) 1 Page - Cirrus Logic |
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SA53 Datasheet(HTML) 1 Page - Cirrus Logic |
1 / 14 page SA53 SA53U P r o d u c t I n n o v a t i o n F r o m DESCRIPTION The SA53 is a fully integrated switching amplifier de- signed primarily to drive DC brush motors. Two inde- pendent half bridges provide over 10 amperes peak output current under microcontroller or DSC control. Thermal and short circuit monitoring is provided, which generates fault signals for the microcontroller to take appropriate action. A block diagram is provided in Fig- ure 1. Additionally, cycle-by-cycle current limit offers user programmable hardware protection independent of the microcontroller. Output current is measured using an innovative low loss technique. The SA53 is built using a multi-technology process allowing CMOS logic con- trol and complementary DMOS output power devices on the same IC. Use of P-channel high side FETs en- ables 60V operation without bootstrap or charge pump circuitry. The Power Quad surface mount package balances ex- cellent thermal performance with the advantages of a low profile surface mount package. FEATURES ♦ Low Cost Intelligent Switching Amplifier ♦ Directly Connects to Most Embedded Micro- controllers and Digital Signal Controllers ♦ Integrated Gate Driver Logic with Dead-time Generation and Shoot-through Prevention ♦ Wide Power Supply Range (8.5 V To 60 V) ♦ Over 10A Peak Output Current per Phase ♦ 3A Continuous Output Current per Phase ♦ Independent Current Sensing for each Output ♦ User Programmable Cycle-by-cycle Current Limit Protection ♦ Over-Current and Over-Temperature Warning Signals APPLICATIONS ♦ Bidirectional DC Brush Motors ♦ 2 Unidirectional DC Brush Motors ♦ 2 Independent Solenoid Actuators ♦ Stepper Motors Switching Amplifier SA53 P r o d u c t I n n o v a t i o n F r o m FIgURE.BLOCKDIAgRAm Copyright © Cirrus Logic, Inc. 2009 (All Rights Reserved) http://www.cirrus.com mAY2009 APEX − SA53UREVA SA53 Switching Amplifier Vs 1 PG ND 1 Gate Control PWM Signals O ut 1 O ut 2 PG ND 2 TEM P GND Vs 2 V S + I LIM/D IS 1 SC DIS2 SG ND Phase 1 Phase 2 Control Logic V DD I1' I2' I1' I2' Fault Logic I1 I2 1t 1b 2t 2b V DD V DD |
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