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AS29LV016 Datasheet(Hoja de datos) 16 Page - Austin Semiconductor

No. de Pieza. AS29LV016
Descripción  16 Megabit (2M x 8-Bit / 1M x 16-Bit) CMOS 3.0 Volt-Only Boot Sector Flash Memory
Descarga  40 Pages
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Fabricante  AUSTIN [Austin Semiconductor]
Página de inicio  http://www.austinsemiconductor.com
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 16 page
background image
CO
CO
CO
CO
COTS PEM
TS PEM
TS PEM
TS PEM
TS PEM
BOO
BOO
BOO
BOO
BOOT SECT
T SECT
T SECT
T SECT
T SECTOR FLASH
OR FLASH
OR FLASH
OR FLASH
OR FLASH
AS29LV016
AS29LV016
Rev. 2.1 10/08
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
16
Austin Semiconductor, Inc.
Table 8: Primary Vendor-Specific Extended Query
Addresses
Addresses
Data
Description
(Word Mode)
(Byte Mode)
40h
80h
0050h
Query-unique ASCII string "PRI"
41h
82h
0052h
42h
84h
0049h
43h
86h
0031h
Major version number, ASCII
44h
88h
0030h
Major version number, ASCII
45h
8Ah
0000h
Address Sensitive Unlock
0=Required, 1=Not Required
46h
8Ch
0002h
Erase Suspend
0=Not Supported, 1=To Read Only, 2=To Read and Write
47h
8Eh
0001h
Sector Protect
0=Not Supported, X=Number of Sectors Per Group
48h
90h
0001h
Sector Temorary Unprotect
00=Not Supported, 01=Supported
49h
92h
0004h
Sector Protect / Unprotect Scheme
01=29F040 mode, 02=29F016 mode,
03=29F400 mode, 04=29LV800A mode
4Ah
94h
0000h
Simultaneous Operation
00=Not Supported, 01=Supported
4Bh
96h
0000h
Burst Mode Type
00=Not Supported, 01= Supported
4Ch
98h
0000h
Page Mode Type
00=Not Supported, 01=4 Word Page, 02= 8 Word Page
HARDWARE DATA PROTECTION
The command sequence requirement of unlock cycles
for programming or erasing provides data protection against
inadvertent writes (refer to Table 9 on page 21 for command
definitions). In addition, the following hardware data
protection measures prevent accidental erasure or
programming, which might otherwise be caused by
spurious system level signals during V
CC power-up and
power-down transitions, or from system noise.
LOW V
CC WRITE INHIBIT
When V
CC is less than VLKO, the device does not accept
any write cycles. This protects data during V
CC power-up
and power-down. The command register and all internal
program/erase circuits are disabled, and the device resets.
Subsequent writes are ignored until V
CC is greater than
V
LKO. The system must provide the proper signals to the
control pins to prevent unintentional writes when V
CC is
greater than V
LKO.
WRITE PULSE
GLITCH PROTECTION
Noise pulses of less than 5 ns (typical) on OE#, CE# or
WE# do not initiate a write cycle.
LOGICAL INHIBIT
Write cycles are inhibited by holding any one of OE# =
V
IL, CE# = VIH or WE# = VIH. To initiate a write cycle,
CE# and WE# must be a logical zero while OE# is a
logical one.
POWER-UP WRITE INHIBIT
If WE# = CE# = V
IL and OE# = VIH during power up, the
device does not accept commands on the rising edge of
WE#. The internal state machine is automatically reset
to reading array data on power-up.




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