AD7780 datasheet(5/16 Pages) AD

No. de pieza	AD7780

Descripción Electrónicos	24-Bit, Pin-Programmable, Ultralow Power Sigma-Delta ADC

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Fabricante Electrónico	AD [Analog Devices]

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AD7780

Rev. A | Page 5 of 16

TIMING CHARACTERISTICS

AVDD = 2.7 V to 5.25 V, DVDD = 2.7 V to 5.25 V, GND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = DVDD, unless otherwise noted.

Table 3.

Parameter1

Limit at TMIN, TMAX

Unit

Test Conditions/Comments

t1

100

ns min

SCLK high pulse width

t2

100

ns min

SCLK low pulse width

t33

0

ns min

SCLK active edge to data valid delay4

60

ns max

DVDD = 4.75 V to 5.25 V

80

ns max

DVDD = 2.7 V to 3.6 V

t4

10

ns min

SCLK inactive edge to DOUT/RDY high

130

ns max

Reset

t5

100

ns min

PDRST low pulse width

t65

FILTER/GAIN change to data valid delay

120

ms typ

Update rate = 16.7 Hz

300

ms typ

Update rate = 10 Hz

1 Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.6 V.

2 See Figure 3.

3 The values of t3 are measured using the load circuit of Figure 2 and are defined as the time required for the output to cross the VOL or VOH limits.

4 SCLK active edge is falling edge of SCLK.

5 The PDRST high to data valid delay is typically 1 ms longer than t6 because the internal oscillator requires time to power up and settle.

Circuit and Timing Diagrams

ISINK (1.6mA WITH DVDD = 5V,

100µA WITH DVDD = 3V)

ISOURCE (200µA WITH DVDD = 5V,

100µA WITH DVDD = 3V)

1.6V

TO

OUTPUT

50pF

Figure 2. Load Circuit for Timing Characterization

DOUT/RDY

(OUTPUT)

MSB

LSB

SCLK

(INPUT)

t3

t1

t4

t2

Figure 3. Read Cycle Timing Diagram

PDRST

(INPUT)

t5

DOUT/RDY

(OUTPUT)

Figure 4. Resetting the AD7780

GAIN OR FILTER

(INPUT)

t6

DOUT/RDY

(OUTPUT)

Figure 5. Changing Gain or Filter Option

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