TIMING DIAGRAMS

t

8

CS

SCLK

InputDataRegisterand

DACLatchUpdated

(1)

DACLatchUpdated

SDI

BIT23(MSB)

BIT23(MSB)

BIT22

BIT1

Low

BIT0

LDAC

t

4

t

1

t

2

t

3

t

F

t

R

t

5

t

6

t

7

Case1:Stand-alonemode,

tiedlow

LDAC

.

CS

SCLK

InputDataRegister Updated

butDACLatchisNotUpdated

SDI

BIT22

BIT1

High

BIT0

LDAC

t

1

t

2

t

3

t

F

t

R

t

7

t

9

Case2:Stand-alonemode,

activehigh.

LDAC

t

10

InputWordToWritetheDatatotheSelectedDAC

=Don’tCare

Bit23=MSB

Bit0=LSB

t

5

t

6

t

8

t

4

TIMING CHARACTERISTICS For Figure 1

(1) (2) (3)

DAC7716

Figure 1. SPI Timing for Stand-Alone Mode

2.7V

2.7V

2.7V

2.7V

PARAMETER

MIN

MAX

MIN

MAX

MIN

MAX

UNIT

Clock frequency

30

40

50

MHz

SCLK cycle time

33

25

20

ns

SCLK high time

16

12

10

ns

SCLK low time

16

12

10

ns

11

9

7

ns

Input data setup time

5

5

5

ns

Input data hold time

5

5

5

ns

SCLK falling edge to CS rising edge

15

12

10

ns

CS high time

60

50

30

ns

CS rising edge to LDAC falling edge

30

25

20

ns

LDAC pulse width

25

20

15

ns

RST pulse width

25

20

15

ns

(1)

Specified by design and characterization.

(2)

Sample tested during the initial release and after any redesign or process changes that may affect these parameters.

(3)

(4)

The first SCLK edge after CS goes low must be a falling edge.

Copyright © 2009, Texas Instruments Incorporated

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