FM32L278/L276/L274/L272 - 3V I2C Companion

Rev. 3.0

Feb. 2009

Page 10 of 21

09h

Watchdog Restart & Flags

D7

D6

D5

D4

D3

D2

D1

D0

WTR

POR

LB

-

WR3

WR2

WR1

WR0

WTR

Watchdog Timer Reset Flag: When a watchdog timer fault occurs, the WTR bit will be set to 1. It must be cleared

by the user. Note that both WTR and POR could be set if both reset sources have occurred since the flags were

cleared by the user. Battery-backed. Read/Write (internally set, user can clear bit).

POR

set to 1. It must be cleared by the user. Note that both WTR and POR could be set if both reset sources have

occurred since the flags were cleared by the user. Battery-backed. Read/Write (internally set, user can clear bit).

LB

Low Backup Flag: On power up, if the VBAK source is below the minimum voltage to operate the event counters,

this bit will be set to 1. The user should clear it to 0 when initializing the system. Battery-backed. Read/Write

(internally set, user can clear bit).

WR3-0

Watchdog Restart: Writing a pattern 1010b to WR3-0 restarts the watchdog timer. The upper nibble contents do

not affect this operation. Writing any pattern other than 1010b to WR3-0 has no effect on the timer. This allows

users to clear the WTR, POR, and LB flags without affecting the watchdog timer. Battery-backed, Write-only.

00-08h

Reserved – DO NOT USE THIS ADDRESS SPACE