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DAC7718SPAGR Datasheet(PDF) 7 Page - Texas Instruments

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No. de pieza DAC7718SPAGR
Descripción Electrónicos  Octal, 12-Bit, Low-Power, High-Voltage Output, Serial Input DIGITAL-TO-ANALOG CONVERTER
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Fabricante Electrónico  TI [Texas Instruments]
Página de inicio  http://www.ti.com
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DAC7718SPAGR Datasheet(HTML) 7 Page - Texas Instruments

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DAC7718
www.ti.com
SBAS467A – MAY 2009 – REVISED DECEMBER 2009
ELECTRICAL CHARACTERISTICS: Single-Supply
All specifications at TA = TMIN to TMAX, AVDD = +32V, AVSS = 0V, IOVDD = DVDD = +5V, REF-A and REF-B = +5V, gain = 6,
AGND-x = DGND = 0V, data format = straight binary, and OFFSET-A = OFFSET-B = AGND, unless otherwise noted.
DAC7718
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
STATIC PERFORMANCE(1)
Resolution
12
Bits
Linearity error
Measured by line passing through codes 010h and FFFh
±1
LSB
Differential linearity error
Measured by line passing through codes 010h and FFFh
±1
LSB
Unipolar zero error
TA = +25°C, gain = 4 or 6, code = 010h
±1
LSB
Unipolar zero error TC
Gain = 4 or 6, code = 010h
±0.5
±3
ppm FSR/°C
TA = +25°C, gain = 6
±1
LSB
Gain error
TA = +25°C, gain = 4
±1
LSB
Gain error TC
Gain = 4 or 6
±1
±3
ppm FSR/°C
Full-scale error
TA = +25°C, gain = 4 or 6, code = FFFh
±1
LSB
Full-scale error TC
Gain = 4 or 6, code = FFFh
±0.5
±3
ppm FSR/°C
Measured channel at code = 800h, full-scale change on any
DC crosstalk(2)
0.05
LSB
other channel
ANALOG OUTPUT (VOUT-0 to VOUT-7)
(3)
VREF = +5V
0
+30
V
Voltage output(4)
VREF = +1.5V
0
+9
V
Output impedance
Code = 800h
0.5
Short-circuit current(5)
±8
mA
Load current
See Figure 84 and Figure 85
±3
mA
TA = +25°C, device operating for 500 hours, full-scale output
3.4
ppm of FSR
Output drift vs time
TA = +25°C, device operating for 1000 hours, full-scale output
4.3
ppm of FSR
Capacitive load stability
500
pF
To 0.03% of FSR, CL = 200pF, RL= 10kΩ, code from 010h to
10
μs
FFFh and FFFh to 010h
To 1 LSB, CL = 200pF, RL = 10kΩ, code from 010h to FFFh
Settling time
15
μs
and FFFh to 010h
To 1 LSB, CL = 200pF, RL = 10kΩ, code from 7F0h to 810h
6
μs
and 810h to 7F0h
Slew rate(6)
6
V/
μs
Power-on delay(7)
From IOVDD ≥ +1.8V and DVDD ≥ +2.7V to CS low
200
μs
Power-down recovery time
90
μs
Digital-to-analog glitch(8)
Code from 7FFh to 800h and 800h to 7FFh
4
nV-s
Glitch impulse peak amplitude
Code from 7FFh to 800h and 800h to 7FFh
5
mV
Channel-to-channel isolation(9)
VREF = 4VPP, f = 1kHz
88
dB
(1)
Gain = 4 and TC specified by design and characterization.
(2)
The DAC outputs are buffered by op amps that share common AVDD and AVSS power supplies. DC crosstalk indicates how much dc
change in one or more channel outputs may occur when the dc load current changes in one channel (because of an update). With
high-impedance loads, the effect is virtually immeasurable. Multiple AVDD and AVSS terminals are provided to minimize dc crosstalk.
(3)
Specified by design.
(4)
The analog output range of VOUT-0 to VOUT-7 is equal to (6 × VREF) for gain = 6. The maximum value of the analog output must not be
greater than (AVDD – 0.5V). All specifications are for a +32V power supply and a 0V to +30V output, unless otherwise noted.
(5)
When the output current is greater than the specification, the current is clamped at the specified maximum value.
(6)
Slew rate is measured from 10% to 90% of the transition when the output changes from 0 to full-scale.
(7)
Power-on delay is defined as the time from when the supply voltages reach the specified conditions to when CS goes low, for valid
digital communication.
(8)
Digital-to-analog glitch is defined as the amount of energy injected into the analog output at the major code transition. It is specified as
the area of the glitch in nV-s. It is measured by toggling the DAC register data between 7FFh and 800h in straight binary format.
(9)
Channel-to-channel isolation refers to the ratio of the signal amplitude at the output of one DAC channel to the amplitude of the
sinusoidal signal on the reference input of another DAC channel. It is expressed in dB and measured at midscale.
Copyright © 2009, Texas Instruments Incorporated
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