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SL15300ZC-XXX Datasheet(PDF) 10 Page - SpectraLinear Inc |
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SL15300ZC-XXX Datasheet(HTML) 10 Page - SpectraLinear Inc |
10 / 16 page Rev 1.0, August 14, 2008 Page 10 of 16 SL15300 Output Rise/Fall Time tr/f2 Programmable, VDD=3.3V, CL=15pF, 20 to 80% of VDD - 2.00 2.40 ns Output Rise/Fall Time tr/f3 Programmable, VDD=3.3V, CL=15pF, 20 to 80% of VDD - 1.40 1.70 ns Output Rise/Fall Time tr/f4 Programmable, VDD=3.3V, CL=15pF, 20 to 80% of VDD - 1.10 1.35 ns Output Rise/Fall Time tr/f5 Programmable, VDD=3.3V, CL=15pF, 20 to 80% of VDD - 0.85 1.00 ns Output Rise/Fall Time tr/f6 Programmable, VDD=3.3V, CL=15pF, 20 to 80% of VDD - 0.70 0.85 ns Output Rise/Fall Time tr/f7 Programmable, VDD=3.3V, CL=15pF, 20 to 80% of VDD - 0.55 0.67 ns Cycle-to-Cycle Jitter (SSCLK – Pins 4/6/7/8) CCJ1 FIN=30MHz, all 4 clocks are at 33MHz, +/-2.0% Spread. CL=15pF - TBD TBD ps Cycle-to-Cycle Jitter (SSCLK – Pins4/6/7/8) CCJ2 FIN=30MHz, all 4 clocks are at 66MHz, +/-2.0% Spread. CL=15pF - TBD TBD ps Power-down Time tPD Time from PD# falling edge to Hi-Z at outputs (Asynchronous) - 150 350 ns Power-up Time (Crystal or Clock) tPU Time from PD# rising edge to valid frequency at outputs (Asynchronous) - 3.5 5.0 ms Power Supply Ramp Time tPSR Time for VDD reaching minimum specified value and monolithic power supply ramp - - 12 ms Output Enable Time tOE Time from OE falling edge to Hi-Z at outputs (Asynchronous) - 180 350 ns Output Disable Time tOD Time from OE falling edge to Hi-Z at outputs (Asynchronous) - 180 350 ns Spread Percent Range SPR-1 Center Spread, SSCLK-1/2/3/4 +/-0.125 - +/-2.5 % Spread Percent Range SPR-2 Down Spread, SSCLK-1/2/3/4 -5.0 - -0.25 % Spread Percent Variation ΔSS% Variation of programmed Spread % -20 - 20 % Modulation Frequency FMOD Programmable, 31.5 kHz standard 25 31.5 120 kHz DC Electrical Characteristics (I-Grade) Unless otherwise stated VDD= 2.5V+/- 10%, CL=15pF and Ambient Temperature range -40 to +85 Deg C Description Symbol Condition Min Typ Max Unit Operating Voltage VDD VDD+/-10% 2.25 2.5 2.75 V Input Low Voltage VIL CMOS Level, if Pins 4 and 8 programmed as PD#, OE, SSON# or FS 0 - 0.3VDD V Input High Voltage VIH CMOS Level, if Pins 4 and 8 programmed as PD#, OE, SSON# or FS. 0.7VDD - VDD V |
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