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SL15316ZC-XXXT Datasheet(PDF) 8 Page - SpectraLinear Inc |
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SL15316ZC-XXXT Datasheet(HTML) 8 Page - SpectraLinear Inc |
8 / 12 page Rev 1.0, August 7, 2008 Page 8 of 12 SL15316 Input Low Current IIL VIN=GND, Pins programmed as PD#, OE, SSON# or FS and no pull-up/down resister used -15 - 15 μA Pull-up or Down Resistors RPU/D Pins programmed as PD#, OE, SSON# or FS 90 150 275 kΩ Operating Supply Current IDD FIN=25MHz Clock, all 5 clocks are at 66MHz, +/-1.0% Spread, CL=0, VDD=VDDO1/2=3.3V - 8.0 TBD mA Standby Current ISBC If programmed PD#=GND - 70 120 μA Output Leakage Current IOL For Pins programmed as SSCLK or REFOUT and if PD# or OE is programmed. PD#=0 or OE=1 -15 - 15 μA Minimum programming value - 7 - pF Programmable Input Capacitance at Pins 3 and 4 PCin PCout Maximum programming value - 38 - pF Input Capacitance CIN2 Pins programmed as PD#, OE, SSON or FS - 4 6 pF Load Capacitance CL For all pins programmed as SSCLK or REFCLK - - 15 pF AC Electrical Characteristics (C and I-Grades) Unless otherwise stated VDD= 2.5V+/- 10% and CL=15pF Parameter Symbol Condition Min Typ Max Unit Input Frequency Range FIN1 Crystal or Ceramic Resonator 8 - 48 MHz Input Frequency Range FIN2 External Clock 3 - 166 MHz Output Frequency Range FOUT1 SSCLK 3 - 200 MHz Output Frequency Range FOUT2 REFCLK, crystal or resonator input 0.25 - 48 MHz Output Frequency Range FOUT3 REFCLK, clock input 0.25 - 166 MHz Output Duty Cycle DC1 SSCLK 45 50 55 % Output Duty Cycle DC2 REFCLK 45 50 55 % Input Duty Cycle DCIN Clock Input, Pin 3 40 50 60 % Output Rise/Fall Time tr/f1 Programmable, VDD=3.3V, CL=15pF, 20 to 80% of VDD - 3.8 - ns Output Rise/Fall Time tr/f2 Programmable, VDD=3.3V, CL=15pF, 20 to 80% of VDD - 1.9 - ns Output Rise/Fall Time tr/f3 Programmable, VDD=3.3V, CL=15pF, 20 to 80% of VDD - 1.4 - ns Output Rise/Fall Time tr/f4 Programmable, VDD=3.3V, CL=15pF, 20 to 80% of VDD - 1.0 - ns Output Rise/Fall Time tr/f5 Programmable, VDD=3.3V, - 0.85 - ns |
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