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74LVC_LVCH1T45_2 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 19 January 2010 3 of 30 NXP Semiconductors 74LVC1T45; 74LVCH1T45 Dual supply translating transceiver; 3-state 5. Functional diagram 6. Pinning information 6.1 Pinning 6.2 Pin description Fig 1. Logic symbol Fig 2. Logic diagram 001aag885 VCC(B) VCC(A) 5 DIR 3 A B 4 001aag886 VCC(B) VCC(A) DIR A B Fig 3. Pin configuration SOT363 (SC-88) Fig 4. Pin configuration SOT886 (XSON6) Fig 5. Pin configuration SOT891 74LVC1T45 74LVCH1T45 VCC(A) VCC(B) GND AB 001aaj991 1 2 3 6 DIR 5 4 74LVC1T45 74LVCH1T45 GND 001aaj992 VCC(A) A DIR VCC(B) B Transparent top view 2 3 1 5 4 6 74LVC1T45 74LVCH1T45 GND 001aaj993 VCC(A) A DIR VCC(B) B Transparent top view 2 3 1 5 4 6 Table 3. Pin description Symbol Pin Description VCC(A) 1 supply voltage port A and DIR GND 2 ground (0 V) A 3 data input or output B 4 data input or output DIR 5 direction control VCC(B) 6 supply voltage port B |
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