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TEA1751T Datasheet(PDF) 8 Page - NXP Semiconductors |
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TEA1751T Datasheet(HTML) 8 Page - NXP Semiconductors |
8 / 29 page TEA1751T_LT_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 23 December 2009 8 of 29 NXP Semiconductors TEA1751T; TEA1751LT GreenChip III SMPS control IC 7.1.4 Fast latch reset In a typical application the mains can be interrupted briefly to reset the latched protection. The PFC bus capacitor, Cbus, does not have to discharge for this latched protection to reset. Typically the PFC bus capacitor, Cbus, has to discharge for the VCC to drop to this reset level. When the latched protection is set, the clamping circuit of the VINSENSE circuit is disabled. (see also Section 7.2.9) As soon as the VINSENSE voltage drops below 750 mV (typical) and after that is raised to 870 mV (typical), the latched protection is reset. The latched protection is also reset by removing both the voltage on pin VCC and on pin HV. 7.1.5 Overtemperature protection An accurate internal temperature protection is provided in the circuit. When the junction temperature exceeds the thermal shutdown temperature, the IC stops switching. As long as OTP is active, the capacitor CVCC is not recharged from the HV mains. The OTP circuit is supplied from the HV pin if the VCC supply voltage is not sufficient. OTP is a latched protection. It can be reset by removing both the voltage on pin VCC and on pin HV or by the fast latch reset function. (See Section 7.1.4) 7.2 Power factor correction circuit The power factor correction circuit operates in quasi-resonant or discontinuous conduction mode with valley switching. The next primary stroke is only started when the previous secondary stroke has ended and the voltage across the PFC MOSFET has reached a minimum value. The voltage on the PFCAUX pin is used to detect transformer demagnetization and the minimum voltage across the external PFC MOSFET switch. 7.2.1 ton control The power factor correction circuit is operated in ton control. The resulting mains harmonic reduction of a typical application is well within the class-D requirements. 7.2.2 Valley switching and demagnetization (PFCAUX pin) The PFC MOSFET is switched on after the transformer is demagnetized. Internal circuitry connected to the PFCAUX pin detects the end of the secondary stroke. It also detects the voltage across the PFC MOSFET. The next stroke is started when the voltage across the PFC MOSFET is at its minimum in order to reduce switching losses and ElectroMagnetic Interference (EMI) (valley switching). If no demagnetization signal is detected on the PFCAUX pin, the controller generates a zero current signal (ZCS), 50 μs (typical) after the last PFCGATE signal. If no valley signal is detected on the PFCAUX pin, the controller generates a valley signal 4 μs (typical) after demagnetization was detected. To protect the internal circuitry during lightning events, for example, it is advisable to add a 5k Ω series resistor to this pin. To prevent incorrect switching due to external disturbance, the resistor should be placed close to the IC on the printed-circuit board. |
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