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6 page 
Rev. 0.3/May. 02 6 HYMD116645B(L)8-M/K/H/L CAPACITANCE (TA=25oC, f=100MHz ) Note : 1. VDD=min. to max., VDDQ=2.3V to 2.7V, VODC=VDDQ/2, VOpeak-to-peak=0.2V 2. Pins not under test are tied to GND. 3. These values are guaranteed by design and are tested on a sample basis only. OUTPUT LOAD CIRCUIT Parameter Pin Symbol Min Max Unit Input Capacitance A0 ~ A11, BA0, BA1 CIN1 58 72 pF Input Capacitance /RAS, /CAS, /WE CIN2 58 72 pF Input Capacitance CKE0 CIN3 58 72 pF Input Capacitance CS0 CIN4 58 72 pF Input Capacitance CK0, /CK0, CK1, /CK1, CK2, /CK2 CIN5 25 40 pF Input Capacitance DM0 ~ DM7 CIN6 812 pF Data Input / Output Capacitance DQ0 ~ DQ63, DQS0 ~ DQS7 CIO1 812 pF VREF VTT RT=50Ω Zo=50Ω CL=30pF Output |
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