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6 page 
HYMD132645D8J Rev. 0.0 / Apr. 2003 6 CAPACITANCE (TA=25 oC, f=100MHz ) Note : 1. VDD = min. to max., VDDQ = 2.5V to 2.7V, VODC = VDDQ/2, VOpeak-to-peak = 0.2V 2. Pins not under test are tied to GND. 3. These values are guaranteed by design and are tested on a sample basis only. OUTPUT LOAD CIRCUIT Parameter Pin Symbol Min Max Unit Input Capacitance A0 ~ A11, BA0, BA1 CIN1 90 104 pF Input Capacitance /RAS, /CAS, /WE CIN2 90 104 pF Input Capacitance CKE0, CKE1 CIN3 58 72 pF Input Capacitance CS0, CS1 CIN4 58 72 pF Input Capacitance CK0, /CK0, CK1, /CK1, CK2,/CK2 CIN5 30 45 pF Input Capacitance DM0 ~ DM7 CIN6 12 17 pF Data Input / Output Capacitance DQ0 ~ DQ63, DQS0 ~ DQS7 CIO1 12 17 pF VREF VTT RT=50Ω Zo=50Ω CL=30pF Output |
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