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6 page 
HYMD216646A(L)6-M/K/H/L Rev. 0.2/May. 02 6 CAPACITANCE (TA=25oC, f=100MHz ) Note : 1. VDD = min. to max., VDDQ = 2.3V to 2.7V, VODC = VDDQ/2, VOpeak-to-peak = 0.2V 2. Pins not under test are tied to GND. 3. These values are guaranteed by design and are tested on a sample basis only. OUTPUT LOAD CIRCUIT Parameter Pin Symbol Min Max Unit Input Capacitance A0 ~ A11, BA0, BA1 CIN1 TBD TBD pF Input Capacitance /RAS, /CAS, /WE CIN2 TBD TBD pF Input Capacitance CKE0 CIN3 TBD TBD pF Input Capacitance CS0 CIN4 TBD TBD pF Input Capacitance CK1, /CK1, CK2, /CK2 CIN5 TBD TBD pF Input Capacitance DM0 ~ DM7 CIN6 TBD TBD pF Data Input / Output Capacitance DQ0 ~ DQ63, DQS0 ~ DQS7 CIO1 TBD TBD pF V REF V TT R T=50Ω Zo=50Ω C L=30pF O utput |
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