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BU9844GUL-W Datasheet(PDF) 7 Page - Rohm |
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BU9844GUL-W Datasheet(HTML) 7 Page - Rohm |
7 / 13 page 7/12 REV. B ◇WP TIMING ○For the WRITE operation, WP must be "LOW" during the period of time from the rising edge of the clock which takes in D0 of first byte until the end of tWR. ( See Fig.-6(a) ) During this period, WRITE operation is canceled by setting WP "HIGH".( See Fig.-6(b) ) ○In the case of setting WP "HIGH" during tWR, WRITE operation is stopped in the middle and the data of accessing address is not guaranteed. Please write correct data again in the case. SCL SDA WP Fig.-6(a) WP TIMING OF THE WRITE OPERATION tHD:WP STOP BIT tWR tHIGH:WP D1 D0 ACK ACK DATA(1) DATA(n) SCL WP SDA D1 D0 ACK ACK DATA(1) DATA(n) tSU:WP Fig.-6(b) WP TIMING OF THE WRITE CANCEL OPERATION |
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