ADF4158CCPZ-RL7 datasheet(4/36 Pages) AD

No. de pieza	ADF4158CCPZ-RL7

Descripción Electrónicos	Direct Modulation/Waveform Generating, 6.1 GHz Fractional-N Frequency Synthesizer

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ADF4158

Rev. 0 | Page 4 of 36

C Version1

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

NOISE CHARACTERISTICS

Normalized Phase Noise Floor4

−213

dBc/Hz

Phase Noise Performance5

@ VCO output

5805 MHz Output6

−93

dBc/Hz

@ 5 kHz offset, 32 MHz PFD frequency

1 Operating temperature for C version: −40°C to +125°C.

2 AC-coupling ensures AVDD/2 bias.

3 Guaranteed by design. Sample tested to ensure compliance.

4 This figure can be used to calculate phase noise for any application. Use the formula –213 + 10 log(fPFD) + 20 logN to calculate in-band phase noise performance as

seen at the VCO output.

5 The phase noise is measured with the EVAL-ADF4158EB1Z and the Agilent E5052A phase noise system.

6 fREFIN = 128 MHz; fPFD = 32 MHz; offset frequency = 5 kHz; RFOUT = 5805 MHz; INT = 181; FRAC = 13631488; loop bandwidth = 100 kHz.

TIMING SPECIFICATIONS

AVDD = DVDD = SDVDD = 2.7 V to 3.3 V; VP = AVDD to 5.5 V; AGND = DGND = SDGND = 0 V; TA = TMIN to TMAX, dBm referred to 50 Ω,

unless otherwise noted.

Table 2. Write Timing

Parameter

Limit at TMIN to TMAX (C Version)

Unit

Test Conditions/Comments

t1

20

ns min

LE setup time

t2

10

ns min

DATA to CLK setup time

t3

10

ns min

DATA to CLK hold time

t4

25

ns min

CLK high duration

t5

25

ns min

CLK low duration

t6

10

ns min

CLK to LE setup time

t7

20

ns min

LE pulse width

Write Timing Diagram

CLK

DATA

LE

DB31 (MSB)

DB30

DB1

(CONTROL BIT C2)

DB2

(CONTROL BIT C3)

DB0 (LSB)

(CONTROL BIT C1)

t1

t2

t3

t7

t6

t4

t5

Figure 2. Write Timing Diagram

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ADF4158CCPZ-RL7 Datasheet(PDF) 4 Page - Analog Devices

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