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74ABT657PW Datasheet(PDF) 4 Page - NXP Semiconductors |
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74ABT657PW Datasheet(HTML) 4 Page - NXP Semiconductors |
4 / 17 page 74ABT657_3 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 03 — 15 March 2010 4 of 17 NXP Semiconductors 74ABT657 Octal transceiver with parity generator/checker; 3-state 5. Pinning information 5.1 Pinning 5.2 Pin description Fig 4. Pin configuration 74ABT657 T/R OE A0 B0 A1 B1 A2 B2 A3 B3 A4 GND VCC GND A5 B4 A6 B5 A7 B6 ODD/EVEN B7 ERROR PARITY 001aae825 1 2 3 4 5 6 7 8 9 10 11 12 14 13 16 15 18 17 20 19 22 21 24 23 Table 2. Pin description Symbol Pin Description T/R 1 transmit/receive input A0 to A7 2, 3, 4, 5, 6, 8, 9, 10 A port input/3-state output VCC 7 positive supply voltage ODD/EVEN 11 parity select input ERROR 12 error output in receive mode PARITY 13 parity output in transmit mode/input in receive mode B0 to B7 23, 22, 21, 20, 17, 16, 15, 14 B port input/3-state output GND 18, 19 ground (0 V) OE 24 output enable input (active LOW) |
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