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74AHCT1G79GV Datasheet(PDF) 7 Page - NXP Semiconductors |
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74AHCT1G79GV Datasheet(HTML) 7 Page - NXP Semiconductors |
7 / 12 page 74AHC_AHCT1G79_5 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 05 — 2 July 2007 7 of 12 NXP Semiconductors 74AHC1G79; 74AHCT1G79 Single D-type flip-flop; positive-edge trigger 12. Waveforms Measurement points are given in Table 9. VOL and VOH are typical output voltage levels that occur with the output. Fig 5. Clock (CP) to output (Q) propagation delay times, clock pulse width, D to set-up times, the CP to D hold times and maximum clock pulse frequency mna647 th tsu th tPHL tW tPLH tsu 1/fmax VM VM VM VI GND VI GND CP input D input VOH VOL Q output Table 9. Measurement points Type Inputs Output VI VM VM 74AHC1G79 GND to VCC 0.5 × V CC 0.5 × V CC 74AHCT1G79 GND to 3.0 V 1.5 V 0.5 × V CC Test data is given in Table 8. Definitions for test circuit: CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. Fig 6. Load circuitry for switching times mna101 VCC VI VO RT CL PULSE GENERATOR DUT |
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