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74AUP1G07GW Datasheet(PDF) 3 Page - NXP Semiconductors |
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74AUP1G07GW Datasheet(HTML) 3 Page - NXP Semiconductors |
3 / 15 page 74AUP1G07_3 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 03 — 17 June 2009 3 of 15 NXP Semiconductors 74AUP1G07 Low-power buffer with open-drain output 6. Pinning information 6.1 Pinning 6.2 Pin description 7. Functional description [1] H = HIGH voltage level; L = LOW voltage level; Z = high-impedance OFF state. Fig 4. Pin configuration SOT353-1 (TSSOP5) Fig 5. Pin configuration SOT886 (XSON6) Fig 6. Pin configuration SOT891 (XSON6) 74AUP1G07 n.c. VCC A GND Y 001aaf412 1 2 3 5 4 74AUP1G07 A 001aaf413 n.c. GND n.c. VCC Y Transparent top view 2 3 1 5 4 6 74AUP1G07 A 001aaf414 n.c. GND n.c. VCC Y Transparent top view 2 3 1 5 4 6 Table 3. Pin description Symbol Pin Description TSSOP5 XSON6 n.c. 1 1 not connected A 2 2 data input GND 3 3 ground (0 V) Y 4 4 data output n.c. - 5 not connected VCC 5 6 supply voltage Table 4. Function table[1] Input Output A Y LL HZ |
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