74AUP1T98GM datasheet(11/17 Pages) NXP

No. de pieza	74AUP1T98GM

Descripción Electrónicos	Low-power configurable gate with voltage-level translator

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Fabricante Electrónico	NXP [NXP Semiconductors]

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11 / 17 page

74AUP1T98_1

Product data sheet

Rev. 01 — 6 March 2008

11 of 17

NXP Semiconductors

74AUP1T98

Low-power conﬁgurable gate with voltage-level translator

[1]

For measuring enable and disable times RL =5kΩ, for measuring propagation delays, setup and hold times and pulse width RL =1MΩ.

Test data is given in Table 11.

Deﬁnitions for test circuit:

RL = Load resistance.

CL = Load capacitance including jig and probe capacitance.

RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.

VEXT = External voltage for measuring switching times.

Fig 13. Load circuitry for switching times

001aac521

DUT

RT

VI

VO

VEXT

VCC

RL

5 k

Ω

CL

G

Table 11.

Test data

Supply voltage

Load

VEXT

VCC

CL

RL[1]

tPLH, tPHL

tPZH, tPHZ

tPZL, tPLZ

2.3 V to 3.6 V

5 pF, 10 pF, 15 pF and 30 pF

5 k

Ω or 1 MΩ

open

GND

2

× VCC

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74AUP1T98GM Datasheet(PDF) 11 Page - NXP Semiconductors

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