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74HCT2G32GD Datasheet(PDF) 3 Page - NXP Semiconductors |
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74HCT2G32GD Datasheet(HTML) 3 Page - NXP Semiconductors |
3 / 13 page 74HC_HCT2G32_3 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 03 — 12 May 2009 3 of 13 NXP Semiconductors 74HC2G32; 74HCT2G32 Dual 2-input OR gate 6.2 Pin description 7. Functional description [1] H = HIGH voltage level; L = LOW voltage level. 8. Limiting values [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] For TSSOP8 package: above 55 °C the value of P tot derates linearly with 2.5 mW/K. For VSSOP8 package: above 110 °C the value of P tot derates linearly with 8 mW/K. For XSON8U package: above 118 °C the value of P tot derates linearly with 7.8 mW/K. Table 3. Pin description Symbol Pin Description 1A, 2A 1, 5 data input 1B, 2B 2, 6 data input GND 4 ground (0 V) 1Y, 2Y 7, 3 data output VCC 8 supply voltage Table 4. Function table[1] Input Output nA nB nY LL L LH H HL H HH H Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit VCC supply voltage −0.5 +7.0 V IIK input clamping current VI < −0.5 V or VI >VCC + 0.5 V [1] - ±20 mA IOK output clamping current VO < −0.5 V or VO >VCC + 0.5 V [1] - ±20 mA IO output current VO = −0.5 V to (VCC + 0.5 V) [1] -25 mA ICC supply current [1] -50 mA IGND ground current [1] −50 - mA Tstg storage temperature −65 +150 °C PD dynamic power dissipation Tamb = −40 °C to +125 °C [2] - 300 mW |
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