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74LVC1G00 Datasheet(PDF) 1 Page - NXP Semiconductors

No. de pieza 74LVC1G00
Descripción Electrónicos  Single 2-input NAND gate
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Fabricante Electrónico  NXP [NXP Semiconductors]
Página de inicio  http://www.nxp.com
Logo NXP - NXP Semiconductors

74LVC1G00 Datasheet(HTML) 1 Page - NXP Semiconductors

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1.
General description
The 74LVC1G00 provides the single 2-input NAND function.
Input can be driven from either 3.3 V or 5 V devices. These features allow the use of these
devices in a mixed 3.3 V and 5 V environment.
Schmitt trigger action at all inputs makes the circuit tolerant for slower input rise and fall
time.
This device is fully specified for partial power-down applications using IOFF.
The IOFF circuitry disables the output, preventing the damaging backflow current through
the device when it is powered down.
2.
Features
s Wide supply voltage range from 1.65 V to 5.5 V
s High noise immunity
s Complies with JEDEC standard:
x JESD8-7 (1.65 V to 1.95 V)
x JESD8-5 (2.3 V to 2.7 V)
x JESD8-B/JESD36 (2.7 V to 3.6 V)
s
±24 mA output drive (V
CC = 3.0 V)
s CMOS low power consumption
s Latch-up performance exceeds 250 mA
s Direct interface with TTL levels
s Inputs accept voltages up to 5 V
s Multiple package options
s ESD protection:
x HBM JESD22-A114E exceeds 2000 V
x MM JESD22-A115-A exceeds 200 V
s Specified from
−40 °Cto+85 °C and −40 °C to +125 °C
74LVC1G00
Single 2-input NAND gate
Rev. 07 — 17 July 2007
Product data sheet


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