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AM1707BZKB4 Datasheet(PDF) 1 Page - Texas Instruments |
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AM1707BZKB4 Datasheet(HTML) 1 Page - Texas Instruments |
1 / 155 page AM1705 www.ti.com SPRS657A – FEBRUARY 2010 – REVISED APRIL 2010 AM1705 ARM Microprocessor Check for Samples: AM1705 1 AM1705 ARM Microprocessor 1.1 Features 123 – 32 Independent DMA Channels • Highlights – 8 Quick DMA Channels – 375/456-MHz ARM926EJ-S™ RISC Core – Programmable Transfer Burst Size – ARM9 Memory Architecture • 128K-Byte RAM Memory – Programmable Real-Time Unit Subsystem • 3.3V LVCMOS IOs (except for USB interface) – Enhanced Direct-Memory-Access Controller 3 (EDMA3) • Two External Memory Interfaces: – Two External Memory Interfaces – EMIFA – Three Configurable 16550 type UART • NOR (8-/16-Bit-Wide Data) Modules • NAND (8-/16-Bit-Wide Data) – Two Serial Peripheral Interfaces (SPI) – EMIFB – Multimedia Card (MMC)/Secure Digital (SD) • 16-Bit SDRAM With 256MB Address Card Interface with Secure Data I/O (SDIO) Space – Two Master/Slave Inter-Integrated Circuit • Three Configurable 16550 type UART Modules: – USB 2.0 OTG Port With Integrated PHY – UART0 With Modem Control Signals – Two Multichannel Audio Serial Ports – 16-byte FIFO – 10/100 Mb/s Ethernet MAC (EMAC) – 16x or 13x Oversampling Option – One 64-Bit General-Purpose Timer • Two Serial Peripheral Interfaces (SPI) Each – One 64-bit General-Purpose/Watchdog Timer With One Chip-Select – Three Enhanced Pulse Width Modulators • Programmable Real-Time Unit Subsystem (PRUSS) – Three 32-Bit Enhanced Capture Modules – Two Independent Programmable Realtime • Applications Unit (PRU) Cores – Industrial Automation • 32-Bit Load/Store RISC architecture – Home Automation • 4K Byte instruction RAM per core – Test and Measurement • 512 Bytes data RAM per core – Portable Data Terminals • PRU Subsystem (PRUSS) can be disabled – Educational Consoles via software to save power – Power Protection Systems – Standard power management mechanism • 375/456-MHz ARM926EJ-S™ RISC Core • Clock gating – 32-Bit and 16-Bit (Thumb®) Instructions • Entire subsystem under a single PSC – Single Cycle MAC clock gating domain – ARM® Jazelle® Technology – Dedicated interrupt controller – EmbeddedICE-RT™ for Real-Time Debug – Dedicated switched central resource • ARM9 Memory Architecture • Multimedia Card (MMC)/Secure Digital (SD) – 16K-Byte Instruction Cache Card Interface with Secure Data I/O (SDIO) – 16K-Byte Data Cache • Two Master/Slave Inter-Integrated Circuit (I2C – 8K-Byte RAM (Vector Table) Bus™) – 64K-Byte ROM • USB 2.0 OTG Port With Integrated PHY (USB0) • Enhanced Direct-Memory-Access Controller 3 – USB 2.0 High-/Full-Speed Client (EDMA3): – USB 2.0 High-/Full-/Low-Speed Host – 2 Transfer Controllers – End Point 0 (Control) 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2 ARM926EJ-S, EmbeddedICE-RT, ETM9, CoreSight are trademarks of ARM Limited. 3 ARM, Jazelle are registered trademarks of ARM Limited. ADVANCE INFORMATION concerns new products in the sampling Copyright © 2010, Texas Instruments Incorporated or preproduction phase of development. Characteristic data and other specifications are subject to change without notice. |
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