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74LVC132AD Datasheet(PDF) 7 Page - NXP Semiconductors |
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74LVC132AD Datasheet(HTML) 7 Page - NXP Semiconductors |
7 / 15 page 74LVC132A_1 © NXP B.V. 2006. All rights reserved. Product data sheet Rev. 01 — 15 December 2006 7 of 15 NXP Semiconductors 74LVC132A Quad 2-input NAND Schmitt trigger Test data is given in Table 8. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig 7. Load circuitry for switching times VM VM tW tW 10 % 90 % 0 V VI VI negative pulse positive pulse 0 V VM VM 90 % 10 % tf tr tr tf 001aae331 VEXT VCC VI VO DUT CL RT RL RL PULSE GENERATOR Table 8. Test data Supply voltage Input Load VEXT VI tr, tf CL RL tPLH, tPHL tPLZ, tPZL tPHZ, tPZH 1.2 V VCC ≤ 2 ns 30 pF 1 k Ω open 2 × VCC GND 1.65 V to 1.95 V VCC ≤ 2 ns 30 pF 1 k Ω open 2 × VCC GND 2.3 V to 2.7 V VCC ≤ 2 ns 30 pF 500 Ω open 2 × VCC GND 2.7 V 2.7 V ≤ 2.5 ns 50 pF 500 Ω open 2 × VCC GND 3.0 V to 3.6 V 2.7 V ≤ 2.5 ns 50 pF 500 Ω open 2 × VCC GND |
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