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74LVC16244ADL Datasheet(PDF) 11 Page - NXP Semiconductors |
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74LVC16244ADL Datasheet(HTML) 11 Page - NXP Semiconductors |
11 / 19 page 74LVC_LVCH16244A_9 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 09 — 18 March 2010 11 of 19 NXP Semiconductors 74LVC16244A; 74LVCH16244A 16-bit buffer/line driver; 5 V input/output tolerant; 3-state [1] The circuit performs better when RL = 1 kΩ. Test data is given in Table 9. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig 9. Load circuit for measuring switching times VM VM tW tW 10 % 90 % 0 V VI VI negative pulse positive pulse 0 V VM VM 90 % 10 % tf tr tr tf 001aae331 VEXT VCC VI VO DUT CL RT RL RL G Table 9. Test data Supply voltage Input Load VEXT VI tr, tf CL RL tPLH, tPHL tPLZ, tPZL tPHZ, tPZH 1.2 V VCC ≤ 2.5 ns 50 pF 500 Ω[1] open 2 × V CC GND 2.7 V 2.7 V ≤ 2.5 ns 50 pF 500 Ω open 2 × V CC GND 3.0 V to 3.6 V 2.7 V ≤ 2.5 ns 50 pF 500 Ω open 2 × V CC GND |
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