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Z0109NA Datasheet(PDF) 2 Page - NXP Semiconductors |
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Z0109NA Datasheet(HTML) 2 Page - NXP Semiconductors |
2 / 12 page Z0109NA_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 4 August 2009 2 of 12 NXP Semiconductors Z0109NA Logic level four-quadrant triac 2. Pinning information 3. Ordering information 4. Limiting values Table 2. Pinning information Pin Symbol Description Simplified outline Graphic symbol 1 T2 main terminal 2 SOT54 (TO-92) 2G gate 3 T1 main terminal 1 1 2 3 sym051 T1 G T2 Table 3. Ordering information Type number Package Name Description Version Z0109NA TO-92 plastic single-ended leaded (through hole) package; 3 leads SOT54 Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VDRM repetitive peak off-state voltage -800 V IT(RMS) RMS on-state current full sine wave; Tlead ≤ 38 °C; see Figure 1 and 4 -1 A dIT/dt rate of rise of on-state current IT =1A; IG =20mA; dIG/dt = 100 mA/µs; T2+ G+ - 50 A/µs IT =1A; IG =20mA; dIG/dt = 100 mA/µs; T2+ G- - 50 A/µs IT =1A; IG =20mA; dIG/dt = 100 mA/µs; T2- G- - 50 A/µs IT =1A; IG =20mA; dIG/dt = 100 mA/µs; T2- G+ - 20 A/µs IGM peak gate current - 1 A PGM peak gate power - 2 W Tstg storage temperature -40 150 °C Tj junction temperature - 125 °C ITSM non-repetitive peak on-state current full sine wave; tp = 20 ms; Tj(init) =25°C; see Figure 2 and 3 -8 A full sine wave; tp = 16.7 ms; Tj(init) =25°C - 8.5 A I2tI2t for fusing tp = 10 ms; sine-wave pulse - 0.32 A2s PG(AV) average gate power - 0.1 W |
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