AD80066

Rev. A | Page 5 of 20

TIMING SPECIFICATIONS

Table 3.

Parameter

Symbol

Min

Typ

Max

Unit

CLOCK PARAMETERS

4-Channel Pixel Rate

166

ns

1-Channel Pixel Rate

83

ns

ADCCLK Pulse Width

20

ns

CDSCLK1 Pulse Width

15

ns

CDSCLK2 Pulse Width

15

ns

CDSCLK1 Falling1 to CDSCLK2 Rising

0

ns

ADCCLK Falling to CDSCLK2 Rising

0

ns

CDSCLK2 Rising to ADCCLK Rising

5

ns

CDSCLK2 Falling1 to ADCCLK Falling

20

ns

CDSCLK2 Falling1 to CDSCLK1 Rising

5

ns

Aperture Delay for CDS Clocks

2

ns

SERIAL INTERFACE

Maximum SCLK Frequency, Write Operation

50

MHz

Maximum SCLK Frequency, Read Operation

25

MHz

SLOAD to SCLK Setup Time

5

ns

SCLK to SLOAD Hold Time

5

ns

SDATA to SCLK Rising Setup Time

2

ns

SCLK Rising to SDATA Hold Time

2

ns

SCLK Falling to SDATA Valid

10

ns

DATA OUTPUT

Output Delay

8

ns

Latency (Pipeline Delay)

3 (fixed)

Cycles

Timing Diagrams

ANALOG

INPUTS

CDSCLK1

CDSCLK2

ADCCLK

OUTPUT

DATA

(D[7:0])

PIXEL n (A,B,C,D)

HIGH

BYTE

LOW

BYTE

HIGH

BYTE

LOW

BYTE

HIGH

BYTE

LOW

BYTE

HIGH

BYTE

LOW

BYTE

HIGH

BYTE

LOW

BYTE

HIGH

BYTE

LOW

BYTE

HIGH

BYTE

HIGH

BYTE

LOW

BYTE

C(n – 2)

B(n – 2)

C(n – 2) D(n – 2) D(n – 2) A(n – 1) A(n – 1) B(n – 1) B(n – 1) C(n – 1) C(n – 1) D(n – 1) D(n – 1)

A(n)

A(n)

B(n)

Figure 3. 4-Channel CDS Mode Timing