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Si5322 Datasheet(PDF) 5 Page - Silicon Laboratories |
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Si5322 Datasheet(HTML) 5 Page - Silicon Laboratories |
5 / 50 page Si5317 Preliminary Rev. 0.15 5 Differential Input Voltage Swing VID fCKIN < 212.5 MHz See Figure 2. 0.2 — — VPP fCKIN > 212.5 MHz See Figure 2. 0.25 — — VPP CKOUT Output Clock1 Common Mode VOCM LVPECL 100 load line-to-line VDD – 1.42 —VDD – 1.25 V Differential Output Swing VOD LVPECL 100 load line-to-line 1.1 — 1.9 VPP Single-ended Output Swing VSE LVPECL 100 load line-to-line 0.5 — 0.93 VPP Differential Output Voltage CKOVD CML 100 load line-to-line 350 425 500 mVPP Common Mode Output Voltage CKOVCM CML 100 load line-to-line —VDD – 0.36 —V Differential Output Voltage CKOVD LVDS 100 load line-to-line 500 700 900 mVPP Low swing LVDS 100 load line-to-line 350 425 500 mVPP Common Mode Output Voltage CKOVCM LVDS 100 load line-to-line 1.125 1.2 1.275 V Output Short to GND CKOISC VDD =3.63V CML, LVDS, LVPECL —80 90 mA VDD =1.89V CML, LVDS —45 50 mA VDD = 3.63 V CMOS — 165 175 mA VDD =1.89V CMOS —65 70 mA Disable — 0.1 0.2 µA Table 2. DC Characteristics (Continued) (VDD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 ºC) Parameter Symbol Test Condition Min Typ Max Units Notes: 1. LVPECL outputs require VDD > 2.25 V. 2. This is the amount of leakage that the 3L inputs can tolerate from an external driver. See Figure 3 on page 9. In most designs, an external resistor voltage divider is recommended. 3. No overshoot or undershoot. |
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