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TMP112AIDRLR Datasheet(PDF) 11 Page - Texas Instruments |
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TMP112AIDRLR Datasheet(HTML) 11 Page - Texas Instruments |
11 / 25 page SERIAL INTERFACE SERIAL BUS ADDRESS BUS OVERVIEW WRITING/READING OPERATION TMP112 www.ti.com ......................................................................................................................................................... SBOS473B – MARCH 2009 – REVISED JUNE 2009 Both operating modes are represented in Figure 13. Table 10 and Table 11 describe the format for the The TMP112 operates as a slave device only on the THIGH and TLOW registers. Note that the most two-wire bus and SMBus. Connections to the bus are significant byte is sent first, followed by the least made via the open-drain I/O lines SDA and SCL. The significant byte. Power-up reset values for THIGH and SDA and SCL pins feature integrated spike TLOW are: suppression filters and Schmitt triggers to minimize • T HIGH = +80°C the effects of input spikes and bus noise. The • T LOW = +75°C TMP112 supports the transmission protocol for both fast (1kHz to 400kHz) and high-speed (1kHz to The format of the data for THIGH and TLOW is the same 3.4MHz) modes. All data bytes are transmitted MSB as for the Temperature Register. first. Table 10. Bytes 1 and 2 of THIGH Register (1) BYTE D7 D6 D5 D4 D3 D2 D1 D0 To communicate with the TMP112, the master must H11 H10 H9 H8 H7 H6 H5 H4 1 first address slave devices via a slave address byte. (H12) (H11) (H10) (H9) (H8) (H7) (H6) (H5) The slave address byte consists of seven address BYTE D7 D6 D5 D4 D3 D2 D1 D0 bits, and a direction bit indicating the intent of H3 H2 H1 H0 0 0 0 0 executing a read or write operation. 2 (H4) (H3) (H2) (H1) (H0) (0) (0) (0) The TMP112 features an address pin to allow up to (1) Extended mode 13-bit configuration shown in parenthesis. four devices to be addressed on a single bus. Table 12 describes the pin logic levels used to Table 11. Bytes 1 and 2 of TLOW Register (1) properly connect up to four devices. BYTE D7 D6 D5 D4 D3 D2 D1 D0 Table 12. Address Pin and Slave Addresses L11 L10 L9 L8 L7 L6 L5 L4 1 DEVICE TWO-WIRE (L12) (L11) (L10) (L9) (L8) (L7) (L6) (L5) ADDRESS A0 PIN CONNECTION BYTE D7 D6 D5 D4 D3 D2 D1 D0 1001000 Ground L3 L2 L1 L0 0 0 0 0 2 1001001 V+ (L4) (L3) (L2) (L1) (L0) (0) (0) (0) 1001010 SDA (1) Extended mode 13-bit configuration shown in parenthesis. 1001011 SCL The device that initiates the transfer is called a Accessing a particular register on the TMP112 is master, and the devices controlled by the master are accomplished by writing the appropriate value to the slaves. The bus must be controlled by a master Pointer Register. The value for the Pointer Register is device that generates the serial clock (SCL), controls the first byte transferred after the slave address byte the bus access, and generates the START and STOP with the R/W bit low. Every write operation to the conditions. TMP112 requires a value for the Pointer Register To address a specific device, a START condition is (see Figure 16). initiated, indicated by pulling the data-line (SDA) from When reading from the TMP112, the last value stored a high to low logic level while SCL is high. All slaves in the Pointer Register by a write operation is used to on the bus shift in the slave address byte on the determine which register is read by a read operation. rising edge of the clock, with the last bit indicating To change the register pointer for a read operation, a whether a read or write operation is intended. During new value must be written to the Pointer Register. the ninth clock pulse, the slave being addressed This action is accomplished by issuing a slave responds to the master by generating an address byte with the R/W bit low, followed by the Acknowledge and pulling SDA low. Pointer Register byte. No additional data are Data transfer is then initiated and sent over eight required. The master can then generate a START clock pulses followed by an Acknowledge Bit. During condition and send the slave address byte with the data transfer SDA must remain stable while SCL is R/W bit high to initiate the read command. See high, because any change in SDA while SCL is high Figure 17 for details of this sequence. If repeated is interpreted as a START or STOP signal. Once all data have been transferred, the master generates a STOP condition indicated by pulling SDA from low to high, while SCL is high. Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Link(s): TMP112 |
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