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TPS2480 Datasheet(PDF) 11 Page - Texas Instruments

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No. de pieza TPS2480
Descripción Electrónicos  Positive Voltage Intelligent Protection Device Hotswap Controller and I2C Current Monitor
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Fabricante Electrónico  TI [Texas Instruments]
Página de inicio  http://www.ti.com
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TPS2480 Datasheet(HTML) 11 Page - Texas Instruments

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LIM
S
50mV
I
R
=
6
F
T
T
C
1347
10
=
´
´
TPS2480
TPS2481
www.ti.com
SLUS939A – APRIL 2010 – REVISED JUNE 2010
ground to alter the natural constant power inrush current shape. If properly designed, the effect is to cause the
leading step of current in Figure 12 to look like a ramp. PROG is internally pulled to ground whenever EN, POR,
or UVLO are not satisfied or the TPS2480 is latched off. This feature serves to discharge any capacitance
connected to the pin. Do not apply voltages greater than 4 V to PROG. If the constant power limit is not used,
PROG should be tied to VREF through a 47-k
Ω resistor.
SCL: This pin is the clock input for the I2C interface.
SDA: This pin is the data input for the I2C interface.
SENSE: Monitors the voltage at the drain of the external FET, and the downstream side of RS providing the
constant power limit engine with feedback of both the external FET current (ID) and voltage (VDS). Voltage is
determined by the difference between SENSE and OUT, while the current analog is the difference between VCC
and SENSE. The constant power engine uses VDS to compute the allowed ID and is clamped to 50 mV, acting
like a traditional current limit at low VDS. The maximum current limit is set by the following equation:
(3)
Design the connections to SENSE to minimize RS voltage sensing errors. Don't drive SENSE to a large voltage
difference from VCC because it is internally clamped to VCC. The current limit function can be disabled by
connecting SENSE to VCC.
TIMER: An integrating capacitor, CT, connected to the TIMER pin provides a timing function that controls the
fault-time for both versions and the restart interval for the TPS2481. The timer charges at 25 mA whenever the
TPS2480/81 is in power limit or current limit and discharges at 2.5 mA otherwise. The charge-to-discharge current
ratio is constant with temperature even though there is a positive temperature coefficient to both. If TIMER
reaches 4 V, the TPS2480 pulls GATE to ground, latches off, and discharges CT. The TPS2491 pulls GATE to
ground and attempt a restart (re-enable GATE) after a timing sequence consisting of discharging CT down to 1 V
followed by 15 more charge and discharge cycles. The TPS2480 can be reset by either cycling the EN pin or the
UVLO (e.g. power cycling). TIMER discharges when EN is low or UVLO or POR are active. The TIMER pin
should be tied to ground if this feature is not used. The general equation for fault retry time as a function of CT is:
(4)
VCC: This pin is associated with three functions:
1. biasing power to the integrated circuit,
2. input to power on reset (POR) and under voltage lockout (UVLO) functions, and
3. voltage sense at one terminal of RS for the external FET current measurement.
The voltage must exceed the POR (about 6 V for roughly 400 ms) and the internal UVLO (about 8 V) before
normal operation (driving the GATE) may begin. Connections to VCC should be designed to minimize RS voltage
sensing errors and to maximize the effect of C1 and D1; place C1 at RS rather than at the device pin to eliminate
transient sensing errors. GATE, PROG, PG, and TIMER are held low when either UVLO or POR are active.
VINM: This pin is Kelvin connected to the negative (load) side of the current sensing resistor. It will appear to
external circuitry as a 20-mA sink in parallel with a 320-kΩ resistor to GND.
VINP: This pin is Kelvin connected to the positive (source) side of the current sensing resistor. It will typically sink
~ 20 mA.
VS: Power source for the logic and I2C interface. Typically between 3 V and 5 V.
VREF: Provides a 4.0-V reference voltage for use in conjunction with the resistor divider of a typical application
circuit to set the voltage on the PROG pin. The reference voltage is available once the internal POR and UVLO
thresholds have been met. It is not designed as a supply voltage for other circuitry, therefore ensure that no more
than 1 mA is drawn. Although not typically required, up to 1000 pF can be placed on this pin.
Copyright © 2010, Texas Instruments Incorporated
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