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CDCE949 Datasheet(PDF) 9 Page - Texas Instruments

No. de pieza CDCE949
Descripción Electrónicos  Programmable 4-PLL VCXO Clock Synthesizer with 1.8V, 2.5V and 3.3V LVCMOS Outputs
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Fabricante Electrónico  TI [Texas Instruments]
Página de inicio  http://www.ti.com
Logo TI - Texas Instruments

CDCE949 Datasheet(HTML) 9 Page - Texas Instruments

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CDCE949
CDCEL949
www.ti.com
SCAS844D – AUGUST 2007 – REVISED MARCH 2010
APPLICATION INFORMATION
Control Terminal Configuration
The CDCE949/CDCEL949 has three user-definable control terminals (S0, S1 and S2) which allow external
control of device settings. They can be programmed to perform any of the following functions:
Spread-Spectrum Clocking selection: Spread-type and spread-amount selection
Frequency selection: Switching between any of two user-defined frequencies
Output-State selection: Output configuration and power-down control
The user can predefine up to eight different control settings. Table 1 and Table 2 explain these settings.
Table 1. Control Terminal Definition
External Control-Bits
PLL1 Setting
PLL2 Setting
PLL3 Setting
PLL4 Setting
Y1 Setting
Control Function
Table 2. PLLx Setting (can be selected for each PLL individual)(1)
SSC Selection (Center/Down)
SSCx [3-bits]
Center
Down
0
0
0
0% (off)
0% (off)
0
0
1
±0.25%
–0.25%
0
1
0
±0.5%
–0.5%
0
1
1
±0.75%
–0.75%
1
0
0
±1.0%
–1.0%
1
0
1
±1.25%
–1.25%
1
1
0
±1.5%
–1.5%
1
1
1
±2.0%
–2.0%
FREQUENCY SELECTION(2)
FSx
FUNCTION
0
Frequency0
1
Frequency1
OUTPUT SELECTION(3) (Y2 ... Y9)
YxYx
FUNCTION
0
State0
1
State1
(1)
Center/Down-Spread, Frequency0/1 and State0/1 are user-definable in PLLx Configuration Register;
(2)
Frequency0 and Frequency1 can be any frequency within the specified fVCO range.
(3)
State0/1 selection is valid for both outputs of the corresponding PLL module and can be power down,
3-state, low or active
Copyright © 2007–2010, Texas Instruments Incorporated
Submit Documentation Feedback
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Product Folder Link(s): CDCE949 CDCEL949


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