Technical Note

7/18

BU7964GUW

www.rohm.com

2010.04 - Rev.A

© 2010 ROHM Co., Ltd. All rights reserved.

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Operation Control

MSDL3 Channel Count Selection

Pins LS0 and LS1 are used to control the high-speed data channel count and data format. High-speed data channel count,

data format should be the same between the transmitting and receiving devices (the BU7963GUW and BU7964GUW,

respectively). Table 6 shows and Receipt Data rate ranges for the LS pin settings.

Table 6. The Range of The Receipt Data rate

LS1

LS0

The Number of Data Channel

The Range of PCLK Input

Frequency [MHz]

The Range of

The Data Receipt Rate

[Mbits/sec]

‘L’

‘L’

1-channel (27-bit format).

4.0-15.0

120-450

‘L’

‘H’

2-channel (27-bit format).

8.0-30.0

240-900

‘H’

‘L’

3-channel (27-bit format).

12.0-45.0

360-1350

CMOS Output Drivability Selection

F_XS determines output drivability of the parallel data interface. Table 7 shows output drivability.

Table 7. Output Drivability

F_XS

Output Drivability

‘L’

1mA Type

‘H’

3mA Type

PLL Bandwidth Selection

BU7964GUW controls the range of the CLK+ / CLK− input frequency (= PCLK output frequency) by the setting of the

data format (LS1, and LS0) of the high-speed data channel and the bandwidth setting of PLL_BW0 and PLL_BW1.

Table 8. PLL Bandwidth Selection

LS1

LS0

PLL_BW1

PLL_BW0

CLK+/CLK- Frequency Range [MHz]

(PCLK Input Frequency)

Min

Max

‘L’

‘L’

‘L’

‘L’

4

7

‘L’

‘L’

‘L’

‘H’

6

11

‘L’

‘L’

‘H’

‘L’

10

15

‘L’

‘H’

‘L’

‘L’

8

14

‘L’

‘H’

‘L’

‘H’

12

22

‘L’

‘H’

‘H’

‘L’

20

30

‘H’

‘L’

‘L’

‘L’

12

21

‘H’

‘L’

‘L’

‘H’

18

33

‘H’

‘L’

‘H’

‘L’

30

45