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Device Address

0

Slave Address

0

1

0

Fixed

Programmable

0

Control Register and Command Byte

B2

B1

B0

B5

B4

B3

B7

B6

TCA6408

WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS

SCPS151C – FEBRUARY 2007 – REVISED JUNE 2007

Interface Definition

BIT

BYTE

7 (MSB)

6

5

4

3

2

1

0 (LSB)

L

H

L

L

L

L

ADDR

R/W

I/O data bus

P7

P6

P5

P4

P3

P2

P1

P0

The address of the TCA6408 is shown in Figure 4.

Figure 4. TCA6408 Address

Address Reference

ADDR

L

32 (decimal), 20 (hexadecimal)

H

33 (decimal), 21 (hexadecimal)

The last bit of the slave address defines the operation (read or write) to be performed. A high (1) selects a read

operation, while a low (0) selects a write operation.

Following the successful acknowledgement of the address byte, the bus master sends a command byte, which

is stored in the control register in the TCA6408. Two bits of this data byte state the operation (read or write) and

the internal registers (input, output, polarity inversion or configuration) that will be affected. This register can be

Figure 5. Control Register Bits

Command Byte

CONTROL REGISTER BITS

COMMAND

POWER-UP

BYTE

REGISTER

PROTOCOL

DEFAULT

B7

B6

B5

B4

B3

B2

B1

B0

(HEX)

0

0

0

0

0

0

0

0

00

Input Port

Read byte

0

0

0

0

0

0

0

1

01

Output Port

Read/write byte

1111 1111

0

0

0

0

0

0

1

0

02

Polarity Inversion

Read/write byte

0000 0000

0

0

0

0

0

0

1

1

03

Configuration

Read/write byte

1111 1111

(1)

Undefined

8

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