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CAT1163LI-28-G Datasheet(PDF) 10 Page - ON Semiconductor |
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CAT1163LI-28-G Datasheet(HTML) 10 Page - ON Semiconductor |
10 / 14 page CAT1163 Doc. No. MD-3003 Rev. I 10 © 2009 SCILLC. All rights reserved. Characteristics subject to change without notice Selective/Random Read Selective/Random READ operations allow the Master device to select at random any memory location for a READ operation. The Master device first performs a ‘dummy’ write operation by sending the START condition, slave address and byte addresses of the location it wishes to read. After the CAT1163 acknowledges, the Master device sends the START condition and the slave address again, this time with the R/W ¯¯ bit set to one. The CAT1163 then responds with its acknowledge and sends the 8-bit byte requested. The master device does not send an acknowledge but will generate a STOP condition. Sequential Read The Sequential READ operation can be initiated by either the Immediate Address READ or Selective READ operations. After the CAT1163 sends the inital 8-bit byte requested, the Master will responds with an acknowledge which tells the device it requires more data. The CAT1163 will continue to output an 8-bit byte for each acknowledge, thus sending the STOP condition. The data being transmitted from the CAT1163 is outputted sequentially with data from address N followed by data from address N+1. The READ operation address counter increments all of the CAT1163 address bits so that the entire memory array can be read during one operation. If more than E (where E=2047 for the CAT1163) bytes are read out, the counter will ‘wrap around’ and continue to clock out data bytes. Manual Reset Operation The CAT116x RESET or RESET ¯¯¯¯¯¯ pin can also be used as a manual reset input. Only the “active” edge of the manual reset input is internally sensed. The positive edge is sensed if RESET is used as a manual reset input and the negative edge is sensed if RESET ¯¯¯¯¯¯ is used as a manual reset input. An internal counter starts a 200ms count. During this time, the complementary reset output will be kept in the active state. If the manual reset input is forced active for more than 200ms, the complementary reset output will switch back to the non active state after the 200ms expired, regardless for how long the manual reset input is forced active. The embedded EEPROM is disabled as long as a reset condition is maintained on any RESET pin. If the external forced RESET/RESET ¯¯¯¯¯¯ is longer than internal controlled time-out period, tPURST, the memory will not respond with an acknowledge for any access as long as the manual reset input is active. Figure 10. Selective Read Timing Figure 11. Sequential Read Timing SLAVE ADDRESS S A C K N O A C K S T O P P BUS ACTIVITY: MASTER SDA LINE S T A R T BYTE ADDRESS (n) S A C K DATA n SLAVE ADDRESS A C K S T A R T BUS ACTIVITY: MASTER SDA LINE DATA n+x DATA n A C K A C K DATA n+1 A C K S T O P N O A C K DATA n+2 A C K P SLAVE ADDRESS |
Número de pieza similar - CAT1163LI-28-G |
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Descripción similar - CAT1163LI-28-G |
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