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M41T60Q6F Datasheet(PDF) 11 Page - STMicroelectronics |
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M41T60Q6F Datasheet(HTML) 11 Page - STMicroelectronics |
11 / 27 page M41T60 Operation Doc ID 10396 Rev 13 11/27 2.3 WRITE mode In this mode the master transmitter transmits to the M41T60 slave receiver. Bus protocol is shown in Figure 10 on page 11. Following the START condition and slave address, a logic '0' (R/W = 0) is placed on the bus and indicates to the addressed device that word address An will follow and is to be written to the on-chip address pointer. The data word to be written to the memory is strobed in next and the internal address pointer is increased to the next address location on the reception of an acknowledge clock. The M41T60 slave receiver will send an acknowledge clock to the master transmitter after it has received the slave address and again after it has received the word address and each data byte. Figure 10. WRITE mode sequence AI00591 BUS ACTIVITY: S P SDA LINE BUS ACTIVITY: MASTER DATA n DATA n+1 DATA n+X WORD ADDRESS (An) SLAVE ADDRESS |
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