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ISLA112P50 Datasheet(PDF) 2 Page - Intersil Corporation |
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ISLA112P50 Datasheet(HTML) 2 Page - Intersil Corporation |
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2 / 35 page  2 FN7604.1 June 17, 2010 Table of Contents Block Diagram ................................................... 1 Pin-Compatible Family....................................... 1 Key Specifications ............................................. 1 Pin Descriptions ................................................ 4 Absolute Maximum Ratings .............................. 5 Thermal Information ........................................ 5 Recommended Operating Conditions ................ 5 Digital Specifications ........................................ 8 Timing Diagrams ............................................... 8 Switching Specifications.................................... 9 Typical Performance Curves ............................ 10 Theory of Operation......................................... 14 Functional Description..................................... 14 Power-On Calibration...................................... 14 User Initiated Reset........................................ 15 Analog Input ................................................. 15 Clock Input ................................................... 16 Jitter ............................................................ 16 Voltage Reference .......................................... 17 Digital Outputs .............................................. 17 Over Range Indicator...................................... 17 Power Dissipation........................................... 17 Nap/Sleep ..................................................... 17 Data Format .................................................. 18 I2E Requirements and Restrictions ................. 19 Overview........................................................ 19 Active Run State ............................................ 19 Power Meter .................................................. 19 FS/4 Filter .................................................... 19 Nyquist Zones............................................... 19 Configurability and Communication .................. 20 Clock Divider Synchronous Reset .................... 20 Serial Peripheral Interface .............................. 22 SPI Physical Interface .................................... 22 SPI Configuration .......................................... 23 Device Information ........................................ 23 Indexed Device Configuration/Control .............. 23 AC RMS Power Threshold................................ 25 Address 0x60-0x64: I2E initialization ............... 26 Device Test................................................... 27 SPI Memory Map ........................................... 28 Equivalent Circuits .......................................... 30 A/D Evaluation Platform ................................. 32 Layout Considerations..................................... 32 Split Ground and Power Planes ........................ 32 Clock Input Considerations ............................. 32 Exposed Paddle ............................................. 32 Bypass and Filtering....................................... 32 LVDS Outputs ............................................... 32 LVCMOS Outputs ........................................... 32 Unused Inputs .............................................. 32 Definitions....................................................... 32 Revision History.................................................. 34 Products.......................................................... 34 Package Outline Drawing ............................... 35 ISLA112P50 |
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