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TS12A44513 Datasheet(PDF) 2 Page - Texas Instruments

No. de pieza TS12A44513
Descripción Electrónicos  LOW ON-STATE RESISTANCE QUAD SPST CMOS ANALOG SWITCHES
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Fabricante Electrónico  TI [Texas Instruments]
Página de inicio  http://www.ti.com
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TS12A44513 Datasheet(HTML) 2 Page - Texas Instruments

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ABSOLUTE MINIMUM AND MAXIMUM RATINGS
(1) (2)
THERMAL IMPEDANCE
TS12A44513
,, TS12A44514,, TS12A44515
SCDS247 – OCTOBER 2008 ............................................................................................................................................................................................. www.ti.com
ORDERING INFORMATION
TA
PACKAGE(1)(2)
ORDERABLE PART NUMBER
TOP-SIDE MARKING
Reel of 2500
TS12A44513DR
TS12A44513
SOIC – D
Reel of 2500
TS12A44514DR
TS12A44514
Reel of 2500
TS12A44515DR
TS12A44515
–40°C to 85°C
Reel of 2000
TS12A44513PWR
YD4513
TSSOP – PW
Reel of 2000
TS12A44514PWR
YD4514
Reel of 2000
TS12A44515PWR
YD4515
(1)
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
(2)
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com.
voltages referenced to GND
MIN
MAX
UNIT
V+
Supply voltage range
–0.3
13
V
VNC
VNO
Analog voltage range(3)
–0.3 V+ + 0.3
V
VCOM
INC
INO
Analog Current range
-20
20
mA
ICOM
Continuous current into any terminal
±20
mA
Peak current, NO or COM (pulsed at 1 ms, 10% duty cycle)
±30
mA
ESD per method 3015.7
2000
V
TA
Operating temperature range
–40
85
°C
D package
1.15
Mounted on JEDEC 4-layer board (JESD
PD
Power dissipation
W
51-7), No airflow, TA = 25°C, TJ = 125°C
PW package
0.88
Tstg
Storage temperature range
–65
150
°C
Lead temperature (soldering, 10 s)
300
°C
(1)
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2)
The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum
(3)
Voltages exceeding V+ or GND on any signal terminal are clamped by internal diodes. Limit forward-diode current to maximum current
rating.
UNIT
D package
133
Mounted on JEDEC 1-layer board (JESD 51-3),
No airflow
PW package
167
Thermal impedance,
θ
JA
°C/W
junction to free air
D package
86
Mounted on JEDEC 4-layer board (JESD 51-7),
No airflow
PW package
112
2
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Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): TS12A44513 TS12A44514 TS12A44515


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