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DAC1408D650_1008 Datasheet(PDF) 11 Page - NXP Semiconductors

No. de pieza DAC1408D650_1008
Descripción Electrónicos  Dual 14-bit DAC up to 650 Msps 2, 4 or 8 interpolating
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Fabricante Electrónico  NXP [NXP Semiconductors]
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DAC1408D650_1008 Datasheet(HTML) 11 Page - NXP Semiconductors

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DAC1408D650
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 02 — 11 August 2010
11 of 98
NXP Semiconductors
DAC1408D650
DAC1408D; up to 650 Msps; 2
×, 4× or 8× interpolating with JESD204A
10. Application information
10.1 General description
The DAC1408D650 is a dual 14-bit DAC operating up to 650 Msps. With a maximum input
data rate of up to 312.5 Msps and a maximum output sampling rate of 650 Msps, the
DAC1408D650 allows more flexibility for wide bandwidth and multi-carrier systems.
Combined with its quadrature modulator and its 32-bit NCO, the DAC1408D650 simplifies
the frequency selection of the system. This is also possible because of the 2
×, 4× or 8×
interpolation filters that remove undesired images.
DAC1408D650 supports the following JESD204A key features:
8-bit/10-bit decoding
Code group synchronization
interlane alignment
scrambling polynomial
Character replacement
TX/RX synchronization management via SYNC signals
Multiple Converter Device Alignment-Multiple Lanes (MCDA-ML) device
DAC1408D650 can be interfaced with any logic device that features high speed SERDES
functionality. This macro is now widely available in FPGA from different vendors.
Standalone SERDES ICs can also be used.
To enhance the intrinsic board layout simplification of the JESD204A standard, NXP
includes polarity swapping for each of the lanes and additionally offers lane swapping.
Each physical lane can be configured as being logically lane0, lane1, lane2 or lane3.
This device is MCDA-ML compliant, offering interlane alignment between several devices.
Samples alignment between devices is maintained up to output level because of an NXP
proprietary mechanism. One device is configured as the master and all the others are
configured as slaves. These will automatically align their output samples to the master
ones. Therefore, a system with several DAC1408D650 can produce data with a
guaranteed alignment of less than 1 DAC output clock period.
Each DAC generates two complementary current outputs on pins IOUTAP/IOUTAN and
IOUTBP/IOUTBN. This provides a full-scale output current of up to 20 mA. An internal
reference is available for the reference current which is externally adjustable using pin
VIRES.
The DAC1408D650 must be configured before operating. Therefore, it features an SPI
slave interface to access internal registers. Some of these registers also provide
information about the JESD204A interface status.
The DAC1408D650 requires both 3.3 V and 1.8 V. 1.8 V has separate digital and analog
power supply pins. The clock input is LVDS compliant.
1x
14
x
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