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SN74AUP1G00DRLRG4 Datasheet(PDF) 2 Page - Texas Instruments

No. de pieza SN74AUP1G00DRLRG4
Descripción Electrónicos  LOW-POWER SINGLE 2-INPUT POSITIVE-NAND GATE
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Fabricante Electrónico  TI [Texas Instruments]
Página de inicio  http://www.ti.com
Logo TI - Texas Instruments

SN74AUP1G00DRLRG4 Datasheet(HTML) 2 Page - Texas Instruments

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† AUP1G08 data at C
L = 15 pF
Output
Input
Switching Characteristics
at 25 MHz
1
A
2
B
Y
4
SN74AUP1G00
SCES604G – SEPTEMBER 2004 – REVISED MARCH 2010
www.ti.com
Figure 1. AUP – The Lowest-Power Family
Figure 2. Excellent Signal Integrity
This single 2-input positive-NAND gate performs the Boolean function Y = A • B or Y = A + B in positive logic.
NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the
package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION(1)
ORDERABLE
TOP-SIDE
TA
PACKAGE(2)
PART NUMBER
MARKING(3)
NanoStar™ – WCSP (DSBGA)
Reel of 3000
SN74AUP1G00YFPR
_ _ _ H A _
0.23-mm Large Bump – YFP (Pb-free)
NanoStar™ – WCSP (DSBGA)
Reel of 3000
SN74AUP1G00YZPR
_ _ _ H A _
0.23-mm Large Bump – YZP (Pb-free)
QFN – DRY
Reel of 5000
SN74AUP1G00DRYR
HA
–40°C to 85°C
uQFN – DSF
Reel of 5000
SN74AUP1G00DSFR
HA
SOT (SOT-23) – DBV
Reel of 3000
SN74AUP1G00DBVR
H00_
SOT (SC-70) – DCK
Reel of 3000
SN74AUP1G00DCKR
HA_
SOT (SOT-553) – DRL
Reel of 4000
SN74AUP1G00DRLR
HA_
(1)
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2)
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
(3)
DBV/DCK/DRL: The actual top-side marking has one additional character that designates the wafer fab/assembly site.
YFP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the wafer fab/assembly site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free).
FUNCTION TABLE
INPUTS
OUTPUT
Y
A
B
L
L
H
L
H
H
H
L
H
H
H
L
LOGIC DIAGRAM (POSITIVE LOGIC)
2
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Copyright © 2004–2010, Texas Instruments Incorporated
Product Folder Link(s): SN74AUP1G00


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