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ISL6113IRZA Datasheet(PDF) 11 Page - Intersil Corporation |
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ISL6113IRZA Datasheet(HTML) 11 Page - Intersil Corporation |
11 / 24 page 11 FN6457.0 September 25, 2007 the ISL6113, ISL6114 respectively, CLOAD is the load capacitance, and CGATE is the total GATE capacitance including CISS of the external MOSFET and any external capacitance connected from the GATE output pin to the GATE reference, GND or source. An estimate for the output slew rate of 3.3V outputs and 12V outputs where there is little or no external 12VGATE output capacitors, can be taken from Equation 2: where ILIM = 50mV/RSENSE and CLOAD is the load capacitance. Note: As a consequence, the CR duration, tFILTER must be programmed to exceed the time it takes to fully charge the output load to the input rail voltage level. MAIN Outputs (Start-up Delay and Slew-Rate Control) The 3.3V outputs act as source followers. In this mode of operation, VSOURCE = [VGATE – VTH(ON)] until the associated output reaches 3.3V. The voltage on the gate of the MOSFET will then continue to rise until it reaches 12V, which ensures minimum rDS(ON). For the 12V outputs, when the MOSFET is optionally configured as a Miller integrator to adjust the VOUT ramp time by having a CGD, which is connected between the MOSFET’s gate and drain. In this configuration, the feedback action from drain to gate of the MOSFET causes the voltage at the drain of the MOSFET to slew in a linear fashion at a rate estimated by Equation 3: Tables 1 and 2 approximate the output slew-rate for various values of CGATE when start-up is dominated by GATE capacitance (external CGATE from GATE pin to ground plus CGS of the external MOSFET for the 3.3V rail; CGD for the 12V rail). During turn-on, the ISL6113 invokes the current regulation (CR) feature to limit inrush current whereas the ISL6114 disables the CR feature during turn-on thus allowing a shorter programmed tFILTER. Both ICs monitor for a severe or Way Overcurrent (WOC) condition such as a short at this time. Note that all of these performance estimates and guidelines are useful only for first order time and loading expectations, as they do not look at other significant loading factors. Figures 3 through 11 realistically illustrate the discussed turn-on performance topic with the noted loading and compensation conditions. Notice the degree of control over the in-rush current and the GATE ramp rate as the CGD and CGS values are changed providing for highly customized turn on characteristics. In some scope shots although the CFILTER shows a ramping in the absence of excessive displayed loading current the CFILTER is responding to the other MAIN supply current that is not displayed. All scope shots were taken from the ISL6113EVAL1Z or ISL6114EVAL1Z platform with any component changes are noted. TABLE 1. ISL6113 3.3V AND 12V OUTPUT SLEW-RATE SELECTION FOR GATE CAPACITANCE DOMINATED START-UP | IGATE | = 25µA CGATE or CGD dv/dt (LOAD) 0.01µF* 2.5V/ms 0.022µF* 1.136V/ms 0.047µF 0.532 V/ms 0.1µF 0.250V/ms *Values in this range will be affected by the internal parasitic capacitances of the MOSFETs used and should be verified empirically. VOUTdv/dt I LIM C LOAD -------------------- = (EQ. 2) VOUTdv/dt 25 μA C GD --------------- = (EQ. 3) ISL6113 VOUTdv/dt 5 μA C GD ------------ = ISL6114 TABLE 2. ISL6114 3.3V AND 12V OUTPUT SLEW-RATE SELECTION FOR GATE CAPACITANCE DOMINATED START-UP | IGATE | = 5µA CGATE or CGD dv/dt (LOAD) 0.01µF* 0.5V/ms 0.022µF* 0.23V/ms 0.047µF 0.106 V/ms 0.1µF 0.050V/ms *Values in this range will be affected by the internal parasitic capacitances of the MOSFETs used and should be verified empirically. FIGURE 3. ISL6113 12VMAIN START-UP RLOAD = 10Ω, CLOAD = 470µF 12 IOUT 12VOUT 12VGATE CFILTER CGD = 6.8nF CGS = 22nF ISL6113, ISL6114 |
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