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ISL22446WFV20Z Datasheet(PDF) 5 Page - Intersil Corporation |
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ISL22446WFV20Z Datasheet(HTML) 5 Page - Intersil Corporation |
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5 / 15 page  5 FN6181.2 September 9, 2009 ILkgDig Leakage Current at Pins SHDN, SCK, SDI, SDO and CS Voltage at pin from GND to VCC -1 1 µA tWRT (Note 21) Wiper Response Time after SPI Write to WR Register 1.5 µs tShdnRec (Note 21) DCP Recall Time from Shutdown Mode From rising edge of SHDN signal to wiper stored position and RH connection 1.5 µs SCK rising edge of last bit of ACR data byte to wiper stored position and RH connection 1.5 µs Vpor Power-on Recall Voltage Minimum VCC at which memory recall occurs 2.0 2.6 V VccRamp VCC Ramp Rate 0.2 V/ms tD Power-up Delay VCC above Vpor, to DCP Initial Value Register recall completed, and SPI Interface in standby state 3ms EEPROM SPECIFICATION EEPROM Endurance 1,000,000 Cycles EEPROM Retention Temperature T < +55°C 50 Years tWC (Note 19) Non-volatile Write Cycle Time 12 20 ms SERIAL INTERFACE SPECIFICATIONS VIL SHDN, SCK, SDI, and CS Input Buffer LOW Voltage -0.3 0.3*VCC V VIH SHDN, SCK, SDI, and CS Input Buffer HIGH Voltage 0.7*VCC VCC + 0.3 V Hysteresis SHDN, SCK, SDI, and CS Input Buffer Hysteresis 0.05*VCC V VOL SDO Output Buffer LOW Voltage IOL = 4mA 0 0.4 V Rpu (Note 20) SDO pull-up resistor off-chip Maximum is determined by tRO and tFO with maximum bus load Cb = 30pF, fSCK = 5MHz 2k Ω Cpin (Note 21) SHDN, SCK, SDI, SDO and CS Pin Capacitance 10 pF fSCK SPI Frequency 5MHz tCYC SPI Clock Cycle Time 200 ns tWH SPI Clock High Time 100 ns tWL SPI Clock Low Time 100 ns tLEAD Lead Time 250 ns tLAG Lag Time 250 ns tSU SDI, SCK and CS Input Setup Time 50 ns tH SDI, SCK and CS Input Hold Time 50 ns tRI SDI, SCK and CS Input Rise Time 10 ns tFI SDI, SCK and CS Input Fall Time 10 20 ns tDIS SDO Output Disable Time 0 100 ns tV SDO Output Valid Time 350 ns Operating Specifications Over the recommended operating conditions, unless otherwise specified. (Continued) SYMBOL PARAMETER TEST CONDITIONS MIN (Note 22) TYP (Note 5) MAX (Note 22) UNIT ISL22446 |
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